Stress-induced voiding in multi-level copper/low-k interconnects

Improved electrical and reliability performance of 65nm interconnects with new barrier integration schemes

“…These thicker Ta layer improves the copper wettability during seed deposition and as a result strengthen the Cu/Ta interface. A better interface limits both vacancies forma- tion under the tensile stress and vacancies diffusion along the interface [5,6]. Meanwhile, the change of via geometry leading to the anchoring of via into the underlying copper line might reduce the local stress which drives the vacancies diffusion [7].…”

Interface Reliability Assessments for Copper/Low-k Products

“…Stress migration via voids are found to be of two basic types with respect to the barrier metal found at the via bottom: 1) voids under a via [28], [34] and 2) voids within a via [34], [46]. The formation of under-via voids has been described as a collection mechanism of excess vacancies that are believed to be stored within the constrained Cu metallization at extended defects such as grain boundaries and interfaces.…”

“…Within-via voiding then will be highly dependent upon the quality of the barrier/seed deposition and subsequent plating steps. Otherwise, pre-existing nanoscopic voids will provide an avenue for further void growth and interconnect failure [40], [46]. Thus, strict interface control of the barrier sidewall coverage of a via is seemingly important to ensure intrinsic reliability and will continue to be a challenge as via diameter and aspect ratio are scaled to keep pace with technology mandates.…”

Study on the Solution of via Bottom Void in 90nm Technology

“…Subsequently, stress-voiding, usually developed during the post electrochemical Cu deposition anneal process, becomes one of the major reliability concerns in Cu dualdamascene interconnect because stress-voids formation in vias induces a drastic increase of via resistance or, in the worst case, via openings. There are two mechanisms of the formation of the stress-voids which were discussed in previous works: if the void is located under via, in the lower Cu line, the nucleation is induced by vacancy accumulation driving by stress gradient [2]; if the void is located inside the via, the nucleation is linked to a local delamination at Cu/Ta interface [3]. In both cases, the void growth is due to the relaxation of tensile stress developed in Cu interconnects [4].…”