Sub-60nm Si tunnel field effect transistors with I&lt;inf&gt;on&lt;/inf&gt; &amp;#x003E;100 &amp;#x00B5;A/&amp;#x00B5;m

Loh, Wei‐Yip; Jeon, Kanghoon; Kang, Chang Yong; Oh, Jungwoo; Patel, Preet; Smith, Casey; Barnett, Joel; Park, Chanro; Liu, Tsu‐Jae King; Tseng, Hsing‐Huang; Majhi, P.; Jammy, R.; Hu, Chenming

doi:10.1109/essderc.2010.5618418

Cited by 13 publications

(8 citation statements)

References 3 publications

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“…As a result, the body of T1 and the gate of T2 (B1/G2) are charged up to the voltage of BL1 with the band-to-band (BTB) tunneling current. The design of the G/S overlap region, which affects the BTB current greatly [11], [13], is very crucial to achieve fast write-"1." As shown in the process scheme, once a poly gate is deposited, a super heavy boron (p ++ ) implantation aligned to the source-side gate edge is implemented before the spacer formation to form a source with dopant density as high as 5 × 10 20 /cm 3 in T1.…”

Section: Fbgc Prototype Fabricationmentioning

confidence: 99%

Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories

Chen

et al. 2012

IEEE Electron Device Lett.

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A capacitorless DRAM cell, floating-body/gate cell (FBGC), is experimentally presented with planar partially depleted SOI CMOS technology. The specially designed gate/drain underlap and gate/source overlap of the first transistor enable long worst case retention time as well as the fast write speed. The operation power dissipation is dramatically reduced while maintaining high sense margin. In addition, FBGC demonstrates excellent endurance performance and nondestructive read operation. Index Terms-Capacitorless DRAM, overlap, SOI floating-body cell (FBC), tunneling field-effect transistor (T-FET), underlap.

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Section: Fbgc Prototype Fabricationmentioning

confidence: 99%

Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories

Chen

et al. 2012

IEEE Electron Device Lett.

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“…Steep switching originating from band-to-band tunneling (BTBT) results in subthreshold swing (SS) values lower than 60 mV=dec, which is the physical limit of MOSFETs at room temperature. [1][2][3][4][5][6][7][8][9][10][11] Thus, TFETs are expected to be building blocks for low-power-consumption large-scale integrated circuits (LSIs).…”

Section: Introductionmentioning

confidence: 99%

Enhancement of capacitance benefit by drain offset structure in tunnel field-effect transistor circuit speed associated with tunneling probability increase

Asai

Mori

Matsukawa

et al. 2018

Jpn. J. Appl. Phys.

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The effect of a drain offset structure on the operation speed of a tunnel field-effect transistor (TFET) ring oscillator is investigated by technology computer-aided design (TCAD) simulation. We demonstrate that the reduction of gate-drain capacitance by the drain offset structure dramatically increases the operation speed of the ring oscillators. Interestingly, we find that this capacitance benefit to operation speed is enhanced by the increase in band-to-band tunneling probability. The "synergistic" speed enhancement by the drain offset structure and the tunneling rate increase will have promising application to the significant improvement of the operation speed of TFET circuits.

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“…Some pioneering research results have been reported for the purpose of low R TUN [3,8]. As a result, recently, I ON of TFETs have risen at a steady pace [9,10]. In particular, III-V TFETs may achieve larger tunneling current compared with Si TFETs due to their smaller bandgap energy and smaller electron mass [11,12].…”

Section: Tunneling-dominant Tfets Vs Drift-dominant Tfetsmentioning

confidence: 99%

Dependency of Tunneling Field-Effect Transistor(TFET) Characteristics on Operation Regions

Lee¹,

Choi²

2011

JSTS:Journal of Semiconductor Technology and Science

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Sub-60nm Si tunnel field effect transistors with I<inf>on</inf> >100 µA/µm

Cited by 13 publications

References 3 publications

Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories

Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories

Enhancement of capacitance benefit by drain offset structure in tunnel field-effect transistor circuit speed associated with tunneling probability increase

Dependency of Tunneling Field-Effect Transistor(TFET) Characteristics on Operation Regions

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