Substrate Engineering for Germanium-Based CMOS Technology

Abstract

Germanium has been proposed as a candidate channel material for high-performance IC devices. The most practical implementation of Ge will be to integrate the material into existing Si-based substrates. Silicon-germanium on insulator (SGOI) has the potential to serve as substrate that can bridge the misfit strain between Ge (or Ge-rich) channel layers for high-mobility pFET devices and strained Si nFET devices. The method of forming SGOI and GeOI using the thermal oxidation approach offers several advantages over competing methods such as wafer bonding. The formation of stacking faults (not oxidation induced) during the relaxation of high Ge content SGOI is suggested to be a significant limitation of this method. The process of SGOI formed by thermal oxidation and its possible use for Ge FET technology development will be critically reviewed.

SiGe Selective Epitaxy: Morphology and Thickness Control for High Performance CMOS Technology

“…To place the images in context, Figure 1 shows a schematic representation of a typical eSiGe device with the key features labeled. Previous papers on SiGe epitaxy have been concerned primarily with the defectivity of the epi layer, or have regarded epi faceting as a problem to be solved (5)(6)(7)(8). We would like to present the epi morphology as a controllable feature, so one may invoke different morphologies as needed to solve different technical problems.…”