Surface State Generation of Mo Gate Metal Oxide Semiconductor Devices Caused by Mo Penetration into Gate Oxide

Abstract

The surface states of molybdenum (Mo) gate metal oxide semiconductor (MOS) devices have been examined and Mo penetration into the Si-Si02 interface during Mo film deposition has been confirmed to be one of the causes of surface state generation. Penetration of Mo atoms occurs when the substrate is heated during deposition by sputtering or electron-beam evaporation. The mechanism responsible for the penetration is assumed to be caused by Mo ions on the Si02 surface during the initial stages of deposition. To prevent this Mo penetration, a very thin Mo film is first deposited at room temperature to form a conductive layer, and a thick Mo film is subsequently deposited at high temperature. By applying th:Ls two-step deposition method, the penetration depth of Mo into the Si02 can be reduced to less than 3 nm and the surface state density can be reduced to below 3 X 1010 cm2 eV even in MOS devices with a gate oxide thickness of 10 nm.

Dual-Metal-Gate Transistors with Symmetrical Threshold Voltages Using Work-Function-Tuned Ta/Mo Bilayer Metal Gates

“…It was reported that the deposition of a Mo gate by sputtering can cause the generation of interface states (D it ) and fixed charges (Q f ) due to the penetration of ionized Mo into SiO 2 . 13) As discussed previously, the diffusion of Ta into the gate dielectrics in the Ta/Mo gate causes a decrease in T inv (À0:17 nm) due to the reaction with SiO 2 as shown in Fig. 9.…”

Reliability Characteristics of W/WN/TaO[sub x]N[sub y]/SiO[sub 2]/Si Metal Oxide Semiconductor Capacitors

“…These results are contrary to the W/TiN/SiO 2 /Si MOS capacitor system, where the interface traps generated during metal gate deposition were reduced with PMA. 10,18 The origins of D it increase in the TaO x N y /SiO 2 and Ta 2 O 5 /SiO 2 system after PMA only are under investigation. It is noted that the D it level is reduced to Ϫ10 11 eV Ϫ1 cm Ϫ2 with additional FGA in Fig.…”

“…8 Other issues of direct metal gates are the metal penetration and plasma damage into the SiO 2 when prepared by the physical vapor deposition ͑PVD͒ method. The damage which is more severe for higher energy sputtering 9 leads to the degradation of reliability, interface, and bulk properties of SiO 2 /Si MOS system; [10][11][12] however, PVD metal gate on the high-k gate dielectric in terms of process-induced damage has not yet been reported.…”

Comparison between chemical vapor deposited and physical vapor deposited WSi2 metal gate for InGaAs n-metal-oxide-semiconductor field-effect transistors

“…5 PVD process is a destructive deposition method which tends to induce damages in the bulk of the oxide and/or oxide/semiconductor interface when the oxide is ultra-thin ͑Ͻ5 nm͒. 6,7 These process-induced defects tend to degrade the MOSFET device performance and reliability. In order to minimize the damages caused by the physical bombardment from the deposited metal atoms, a less destructive deposition method such as chemical vapor deposition ͑CVD͒ is required as an alternative for the metal gate deposition.…”