Switched-current circuits in digital CMOS technology with low charge-injection errors

Balachandran, Ganesh K.; Allen, P.E.

doi:10.1109/jssc.2002.803019

Cited by 31 publications

(11 citation statements)

References 12 publications

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“…This confirms the satisfactory precision of the operation of the designed integrator. It is shown in [13] that filters realized with the use of the integrator can perform better than filters presented in the literature [10] by one order of magnitude in power consumption and chip area.…”

Section: Resultsmentioning

confidence: 99%

Low power switched‐current circuits with low sensitivity to the rise/fall time of the clock

Rudnicki¹,

Kropidłowski²,

Handkiewicz³

2008

Circuit Theory & Apps

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SUMMARYThe switched-current (SI) technique permits realizing analog discrete-time circuits in standard digital CMOS technology. A very important property of the analog part of a system on a chip is the possibility it offers for realizing some functions of a digital circuit, but with reduced power consumption. In this paper, a low power SI integrator is presented. It is shown that an integrator consuming a fraction of a milliwatt can be designed in 0.35 m CMOS technology with the use of narrow transistor channels, and with the channel length as a design parameter. The impact of the rise/fall time of the clock signal on the integrator operation is observed. It is shown that this effect can be reduced when the proper switch dimensions are taken for the integrator. Analysis and measurements of the integrator noise are presented. The integrator was built with equal size transistors, yielding less sensitivity to variations in production parameters. An experimental chip in 0.35 m CMOS technology was fabricated, and measurements are compared with results obtained during analysis and simulations. In order to verify the properties of the designed integrator experimentally, a first-order filter is built with the use of elementary cells on the chip.

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Section: Resultsmentioning

confidence: 99%

Low power switched‐current circuits with low sensitivity to the rise/fall time of the clock

Rudnicki¹,

Kropidłowski²,

Handkiewicz³

2008

Circuit Theory & Apps

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“…These error voltages will be seen as a common mode signal and suppressed by the common mode rejection capability of the . As a result, a high linearity CSH circuit is obtained [5], [8], [12], [13]. It is worth to note that even in the situation that both are nonlinear, the complete error cancellation mentioned above can be achieved as long as the and are identical and the former are linear, and the sampling period is sufficiently long for complete settling of .…”

Section: Capacitormentioning

confidence: 99%

“…This argument becomes clearer when we operate the transconductors in a negative feedback fashion as transimpedance amplifiers by applying input current , taking output voltage and observing the behavior of for the entire range of the varied . Hence, the output currents and the input voltages of the transconductors become input and output variables, respectively, and (4) and (5) are rewritten as (12) and (13) for the case of class-A and class-AB, respectively. These transfer characteristics are plotted and shown in Fig.…”

Section: B Signal Excursion and Drivabilitymentioning

confidence: 99%

Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit

Sawigun

Serdijn

2011

IEEE Trans. Circuits Syst. I

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This paper proposes the design of a current-mode sample and hold circuit using subthreshold MOSFETs. The proposed circuit combines negative feedback and the compressive characteristic of a class-AB weak inversion transconductor to achieve low switching error, high signal-to-noise ratio and high dynamic range from a low supply voltage and very low current consumption. The paper also provides a feedback analysis of current mode sample and hold circuits. Several design issues including circuit stability, mismatch, linearity, noise, and power consumption are discussed and a comparison of class-A and class-AB versions of subthreshold sample and hold circuits is made. The design verification of the proposed class-AB current mode sample and hold circuit is done by circuit simulations using 0.13 m CMOS model parameters. The results show that, from a 0.6 V supply and with a power consumption of 27.5 nW, the proposed circuit provides 73 dB signal-to-noise ratio, 77 dB dynamic range, and a figure of merit of 1.9 nW/MHz.

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“…Current mode signal processing implemented in CMOS technology has received increasing interest in the past decades [1][2][3] . The circuit implemented in current mode technique occupies small area, consumes less power dissipation and achieves high operation speed.…”

Section: Introductionmentioning

confidence: 99%

Power efficient high speed switched current comparator

Sun

Lai

2007

2007 7th International Conference on ASIC

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A power efficiency improved switched current comparator based on Boonsobhak's comparator is presented. Controlled by two complementary clock signals, the proposed comparator operates in a master and slave manner. The master comparator not only generates a voltage difference according to the input current, but also isolate the input terminal from the output signals to prevent extreme voltage surge, or kickback noise, while the slave comparator is allowed to regenerate and produce a valid digital output. Employing a static class AB latched comparator as the master comparator and a 0-static-power-dissipated dynamic latched comparator as the slave one; the proposed current comparator achieves high power efficiency and high speed. Designed and simulated in TSMC 0.25 m mixed signal CMOS technology with 1.8V supply voltage, the proposed SI comparator achieves a current sensitivity up to 0.2µA, and a sampling frequency up to 400MHz, with 30% power reduction compared to the original one.

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Switched-current circuits in digital CMOS technology with low charge-injection errors

Cited by 31 publications

References 12 publications

Low power switched‐current circuits with low sensitivity to the rise/fall time of the clock

Low power switched‐current circuits with low sensitivity to the rise/fall time of the clock

Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit

Power efficient high speed switched current comparator

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