Techniques for on-chip process voltage and temperature detection and compensation

Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology

“…These hazards will become even worse if the nanomerer CMOS technology is used and PVT variations appear [13][14][15][16]. However, most of the prior designs did not consider the slew rate deviation caused by the PVT variation [17][18][19][20][21][22]. In fact, PVT variations have been proved to affect the slew rate of the output buffer severely, as shown in Fig.…”

“…Thus, many recent works have been proposed to enhance the capability against PVT variation and enlarge the acceptable envelope as much as possible to elevate the yield. Though delay-based methods have been widely utilized to the detect PVT variation [18,23], those methods can only recognize three corners, i.e., TT, FF, and SS. The FS and SF corners were left unsolved in these works.…”