Thermal management of 3D IC integration with TSV (through silicon via)

Lau, John H.; Yue, Tang Gong

doi:10.1109/ectc.2009.5074080

Cited by 153 publications

(60 citation statements)

References 11 publications

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“…Therefore we propose a formula regarding the silicon substrate as a parallel plate capacitor that considers the effective volume of the silicon substrate between two TSVs. In equations (2), and (3), we use scaling factors (α) which has the value of 24µm. TSVs is 10µm.…”

Section: Electrical Model Of Tsvsmentioning

confidence: 99%

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Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs

Song

Liu

Kim

et al. 2011

2011 12th International Symposium on Quality Electronic Design

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Abstract-It is widely-known that coupling exists between adjacent through-silicon vias (TSVs) in 3D ICs. Since this TSVto-TSV coupling is not negligible, it is highly likely that TSVto-TSV coupling affects crosstalk significantly. Although a few works have already analyzed coupling in 3D ICs, they used Sparameter-based methods under the assumption that all ports in their simulation structures are under 50-Ω termination condition. However, this 50-Ω termination condition does not occur at ports (pins) of gates inside a 3D IC. In this paper, therefore, we analyze TSV-to-TSV coupling in 3D ICs based on a lumped circuit model with a realistic high-impedance termination condition. We also analyze how channel affect TSV-to-TSV coupling differently in different frequency ranges. Based on our results, we propose a technique to reduce TSV-to-TSV coupling in 3D ICs.

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Section: Electrical Model Of Tsvsmentioning

confidence: 99%

“…TSVs are much smaller than off-chip wires, thereby enabling very wide bandwidth and high-speed communication between stacked dies. However, there exist several problems such as heat, TSV defects, and power delivery in 3D ICs [2], [3]. These problems need to be resolved to build reliable 3D ICs.…”

Section: Introductionmentioning

confidence: 99%

Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs

Song

Liu

Kim

et al. 2011

2011 12th International Symposium on Quality Electronic Design

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“…In addition to the parameters used in Lau and Yue, [9] Table 1 has also included the parameter of SiO2 thickness, which results in a smaller planar equivalent thermal conductivity and a larger vertical equivalent thermal conductivity of TSV cell than the isotropic thermal conductivity of silicon. The studies of Chien et al [1,2] derived the empirical correlations of equivalent TSV thermal conductivities in planar and vertical directions.…”

Section: Introductionmentioning

confidence: 99%

“…[3] Using the TSVs, a conventional IC design can be divided into two or analysis in design phases. Lau and Yue [9] studied the equivalent thermal conductivities in planar and vertical directions for 3D IC structure with TSVs embedded in stacked chips in simulations. The simulation results of equivalent thermal conductivities are for the entire chip embedded with TSVs.…”

Section: Introductionmentioning

confidence: 99%

“…[6,7] Experiment results and simulation analyses have also been reported, especially for the TSV thermal behavior. [4,5,8,9] Oprins et al [8] has designed and fabricated a test chip as well as conducted the measurements of thermal performance for the test vehicle, which one thinned chip with TSV is bonded on top of a thick chip without TSV using Rm.168, Bldg.14, No.195, Sec. 4, Chung Hsing Road, Chutung, Hsinchu 31040, Taiwan (Received July 23, 2012; accepted November 5, 2012) Abstract A two-chip stacking 3D IC with 0.18 μm technology has been mounted in a QFP package for conducting measurement of thermal resistance from junction to the package case surface (bottom).…”

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confidence: 99%

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Thermal Performance of 3D IC Package with Embedded TSVs

Tain

Dai

Chao

et al. 2012

Transactions of The Japan Institute of Electronics Packaging

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more than two chips and these IC chips can be stacked up vertically and communicate with each other through vias.However, thermal challenge of the 3D IC chip stack becomes a limitation for using the TSVs because the heat spreading in the stack is less effective than non-stacked chips. [4,5] Therefore, thermal performance is the major concern for vertical IC chip stack. TSV is a metal-filled component embedded in a silicon chip, where a dielectric layer (e.g. silicon dioxide, SiO 2 ) is deposited between the bulk silicon and the metal filling. The thermal conductivity of SiO2 layer is orders of magnitude less than that of metal filling, e.g. the copper. Thus, the thermal property for a TSV or a TSV group is much better in vertical direction than in the planar direction.Thermal solutions for stacked IC structure have been proposed and investigated from literature. [6,7] Experiment results and simulation analyses have also been reported, especially for the TSV thermal behavior. [4,5,8,9] Oprins et al. [8] has designed and fabricated a test chip as well as conducted the measurements of thermal performance for the test vehicle, which one thinned chip with TSV is bonded on top of a thick chip without TSV using Rm.168, Bldg.14, No.195, Sec. 4, Chung Hsing Road, Chutung, Hsinchu 31040, Taiwan (Received July 23, 2012; accepted November 5, 2012) Abstract A two-chip stacking 3D IC with 0.18 μm technology has been mounted in a QFP package for conducting measurement of thermal resistance from junction to the package case surface (bottom). The thermal resistances for the layers of chips, micro bumps, underfill resin between chips, and ceramic substrate are also being analyzed with the thermal RC model theory and the cumulative structure function. The top chip is embedded with through-silicon vias (TSVs) and is thinned down to 60 μm thick. The bottom chip has no TSV and the thickness is the same as a normal IC chip. Both chips have the same layout and include two types of heaters. The first heater is designed to emulate a hot spot and is located at the chip center. The second heater, with heat flux level (uniform heating) close to 1/20 of the first heater, is designed to heat up the surrounding area of the first heater. A simulation model of the QFP package is developed and a set of equivalent thermal conductivity correlations in planar (xy) and vertical (z) directions of TSVs are used in order to simplify the simulation model and shorten the computational time. Comparisons between simulation models show that the result is accurate for uniform heating condition and satisfactory for hot spot heating condition.Keywords: 3D IC, Through Silicon Via, Chip Stacking, Thermal Conductivity, QFP Package 76Transactions of The Japan Institute of Electronics Packaging Vol. 5, No. 1, 2012 analysis in design phases. Lau and Yue[9] studied the equivalent thermal conductivities in planar and vertical directions for 3D IC structure with TSVs embedded in stacked chips in simulations. The simulation results of equivalent thermal conducti...

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Fundamentals of Heat Dissipation in 3D IC Packaging

Kandlikar

Ganguly

2017

3D Microelectronic Packaging

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Thermal management of 3D IC integration with TSV (through silicon via)

Cited by 153 publications

References 11 publications

Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs

Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs

Thermal Performance of 3D IC Package with Embedded TSVs

Fundamentals of Heat Dissipation in 3D IC Packaging

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