Thermal stress and reliability characterization of barriers for Cu interconnects

Musaka, K.; Zheng, Baolong; Wang, H.; Wijkekoon, K.; Chen, L.; Lin, J.H.; Watanabe, K.; Ohira, Kentaro; Hosoda, Toru; Miyata, Kouji; Hasegawa, T.; Dixit, G.; Chueng, Roy; Yamada, M.; Kadomura, S.

doi:10.1109/iitc.2001.930024

Cited by 8 publications

(8 citation statements)

References 3 publications

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“…Figure 12 shows the SIV test results as a function of linewidth, compared with the D/D structure. 5) The SIV failure characteristics slightly differ between the S/D and D/ Both analyzed samples were obtained after the via resistance had become higher. As shown in these images, the failure modes are the same.…”

Section: Interconnect Reliabilitymentioning

confidence: 94%

“…We considered that a widely used dual damascene (D/D) structure also suffered from Cu void generation due to a stress migration phenomenon. 5,6) This Cu void generation problem was considered to become increasingly severe when via size decreased. We adopted a new process and a material-oriented design concept in order to construct a robust multilevel interconnect structure timely.…”

Section: Introductionmentioning

confidence: 99%

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A Robust Embedded Ladder-Oxide/Cu Multilevel Interconnect Technology for 0.13 µm Complementary Metal Oxide Semiconductor Generation

Oda

Itô

Takewaki

et al. 2007

jjap

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A robust embedded ladder-oxide (k ¼ 2:9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 mm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 mm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO 2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.

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Section: Interconnect Reliabilitymentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

A Robust Embedded Ladder-Oxide/Cu Multilevel Interconnect Technology for 0.13 µm Complementary Metal Oxide Semiconductor Generation

Oda

Itô

Takewaki

et al. 2007

jjap

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“…More conformal barriers will become necessary for adequate step coverage in high aspect ratio vias and trenches. Extensive work has been done in developing novel barrier materials and associated deposition modes to address the conformality requirements in aggressive device features (2,3,4). CVD barrier materials have emerged as viable technology solutions, with TiSiN showing particular commercial promise.…”

Section: Introductionmentioning

confidence: 99%

CVD TiSiN diffusion barrier integration in sub-130 mn technology nodes

Prindle

Brennan²,

Denning³

et al. 2002

Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519)

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Metalorganic chemical vapor deposition (MOCVD) titanium silicon nitride (TiSiN) has emerged as a strong candidate for a next-generation diffusion barrier material in copper/low-k dielectric back-end-of-line (BEOL) device fabrication. As ionized physical vapor deposition (PVD) Ta(N) barriers currently used in high-volume production begin to exhibit marginal film continuity in high aspect ratio device features, more conformal barrier materials become a requirement. Material, electrical, and reliability properties are strongly influenced by CVD TiSiN film thickness, process sequencing, and incoming surface cleanliness of device features. TiSiN has been shown to possess the necessary material and electrical properties to be successfully integrated in sub-130 nm copper/low-k semiconductor device technology nodes.

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“…Therefore, many issues related to this process have been studied in detail. [1][2][3][4][5] Some of these issues affect the yield of the via chain. [4][5][6] The first via approach for the dual damascene structure consists of the following sequence.…”

mentioning

confidence: 99%

“…[1][2][3][4][5] Some of these issues affect the yield of the via chain. [4][5][6] The first via approach for the dual damascene structure consists of the following sequence. ͑i͒ Via etching through the whole dielectric stack (trench ϩ via), and then bottom antireflective coating ͑BARC͒ via filling, (ii) trench lithography, (iii) BARC etch back, (iv) trench etching in fluorinated silicate glass ͑FSG͒, and then O 2 -based plasma cleaning, and (v) capping nitride removal, and then O 2 -based plasma cleaning.…”

mentioning

confidence: 99%

Avoiding Cu Hillocks during the Plasma Process

Kang

Chou

2004

J. Electrochem. Soc.

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When Cu wafers are exposed to H 2 /N 2 plasma, hillocks are formed on the Cu wafer surface by a plasma cleaner with a surface wave plasma source. Plasma cleaning is divided into the initial stage and the rising temperature stage. Under a supply of H 2 /N 2 gas and with the plasma power turned on, the H radicals first restore native copper oxide to pure copper. The N radicals then compete with the H radicals, and diffuse to the Cu grain boundary, which is the initial stage. During the rising temperature stage, plasma energy is absorbed by the Cu surface, and the wafer temperature increases rapidly. Consequently, plasma-enhanced compressive stress leads to the formation of Cu hillocks. For a plasma with a higher N/H radical ratio, more N radicals diffusing to the Cu grain boundary results in more Cu-N compounds, which make up the main source of stress during H 2 /N 2 plasma cleaning. Experimental results indicate that using a plasma cleaner with an inductively coupled plasma source can achieve a lower N/H radical ratio, thus avoiding the formation of Cu hillocks.The Cu dual damascene process has been widely employed for fabricating multilevel interconnection schemes in ultralarge scale integration ͑ULSI͒ circuits. This is because Cu dual damascene wiring provides significant advantages over the conventional Al metallization process. Therefore, many issues related to this process have been studied in detail. 1-5 Some of these issues affect the yield of the via chain. 4-6 The first via approach for the dual damascene structure consists of the following sequence. ͑i͒ Via etching through the whole dielectric stack (trench ϩ via), and then bottom antireflective coating ͑BARC͒ via filling, (ii) trench lithography, (iii) BARC etch back, (iv) trench etching in fluorinated silicate glass ͑FSG͒, and then O 2 -based plasma cleaning, and (v) capping nitride removal, and then O 2 -based plasma cleaning. The schematic process is shown in Fig. 1. Sometimes, it is difficult to stop the etch on the thin nitride film during via etching due to low or unstable oxide/nitride selectivity. Therefore, the Cu underlayer will be exposed to air after via etching. Moreover, it is observed that using only wet solvent cleaning after nitride removal will result in some residue, as shown in Fig. 2. Therefore, it is also necessary to use plasma cleaning after nitride removal. For conventional postetch cleaning technology used in the Al interconnection process, most recipes use O 2 -based plasma with high temperatures of 250-275°C. Even though the Al underlayer is exposed to air after via or trench etching, it is notable that the thin Al 2 O 3 compound on Al surfaces is not oxidized continuously during O 2 -based plasma cleaning. However, the weak Cu oxide on the Cu surface cannot provide an effective barrier to prevent Cu bulk from continuous oxidization at high temperature. These copper oxides may possibly cause difficulty in subsequent cleaning and reduction in interconnection yield. Therefore developing a new dry cleaning technology for Cu dual...

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Thermal stress and reliability characterization of barriers for Cu interconnects

Cited by 8 publications

References 3 publications

A Robust Embedded Ladder-Oxide/Cu Multilevel Interconnect Technology for 0.13 µm Complementary Metal Oxide Semiconductor Generation

A Robust Embedded Ladder-Oxide/Cu Multilevel Interconnect Technology for 0.13 µm Complementary Metal Oxide Semiconductor Generation

CVD TiSiN diffusion barrier integration in sub-130 mn technology nodes

Avoiding Cu Hillocks during the Plasma Process

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