Thermally Assisted Nonvolatile Memory in Monolayer MoS<sub>2</sub> Transistors

He, Guowei; Ramamoorthy, H.; Kwan, C.-P.; Lee, Y.-H.; Nathawat, J.; Somphonsane, R.; Morikura, Masahiro; Higuchi, Ayaka; Yamanaka, Toshiaki; Aoki, Nobuyuki; Gong, Yuefeng; Zhang, X.; Vajtai, Róbert; Ajayan, Pulickel M.; Bird, J. P.

doi:10.1021/acs.nanolett.6b02905

Cited by 53 publications

(67 citation statements)

References 37 publications

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“…2d, indicating hysteresis inversion. The hysteresis direction (clockwise at room temperature 18,22,23 and anti-clockwise at high temperature 29 ) is the same as stated in earlier reports. However, the reasons given for hysteresis in these reports such as adsorbates, oxide and interface traps do not explain hysteresis inversion and its reversibility.…”

Section: Resultssupporting

confidence: 82%

“…1d) reinforce the presence of intrinsic traps/defects in the multilayer MoS 2 channel, which could be both, interlayer and intralayer defects (i.e. atomic point defects such as molybdenum and/or sulfur vacancies), unlike monolayer MoS 2 which does not show any clockwise hysteresis at room temperature 29 likely due to the absence of interlayer traps and smaller number of intralayer defects. The advantage of using R A /R C measurements is that they allow the gate-dependent homogeneity of charges to be determined.…”

Section: Resultsmentioning

confidence: 72%

“…molybdenum and/ or sulfur vacancies 28 ) at room temperature, and the second due to extrinsic charge exchange between SiO 2 and p + Si gate at higher temperatures (>350 K). 29 Trap time constants at different temperatures were extracted using pulsed I-V measurements. Moreover, trap densities in MoS 2 and the gate oxide were extracted from the experimental data and used in simulations to reproduce the experimental inversion of hysteresis, thereby validating the intrinsic-oxide trap model.…”

Section: Introductionmentioning

confidence: 99%

“…29 The requirement of high temperature (495 K) 29 to perform read and write operations is still a roadblock for the realization of fully functional heat-assisted memories. By exploiting hysteresis and its inversion, we have demonstrated thermally assisted programmable non-volatile memory at a much lower temperature (375 K) than previously reported.…”

Section: Introductionmentioning

confidence: 99%

“…By exploiting hysteresis and its inversion, we have demonstrated thermally assisted programmable non-volatile memory at a much lower temperature (375 K) than previously reported. 29 Further, the variation in difference of forward (FS) and reverse sweep (RS) conductances over a wide temperature range of 100 K, as well as the reversibility of the hysteresis, can be harnessed for temperature sensing applications.…”

Section: Introductionmentioning

confidence: 99%

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Reversible hysteresis inversion in MoS2 field effect transistors

et al. 2017

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The origin of threshold voltage instability with gate voltage in MoS 2 transistors is poorly understood but critical for device reliability and performance. Reversibility of the temperature dependence of hysteresis and its inversion with temperature in MoS 2 transistors has not been demonstrated. In this work, we delineate two independent mechanisms responsible for thermally assisted hysteresis inversion in gate transfer characteristics of contact resistance-independent multilayer MoS 2 transistors. Variable temperature hysteresis measurements were performed on gated four-terminal van der Pauw and two-terminal devices of MoS 2 on SiO 2 . Additional hysteresis measurements on suspended (~100 nm air gap between MoS 2 and SiO 2 ) transistors and under different ambient conditions (vacuum/nitrogen) were used to further isolate the mechanisms. Clockwise hysteresis at room temperature (300 K) that decreases with increasing temperature is shown to result from intrinsic defects/traps in MoS 2 . At higher temperatures a second, independent mechanism of charge trapping and de-trapping between the oxide and p + Si gate leads to hysteresis collapse at~350 K and anti-clockwise hysteresis (inversion) for temperatures >350 K. The intrinsic-oxide trap model has been corroborated through device simulations. Further, pulsed current-voltage (I-V) measurements were carried out to extract the trap time constants at different temperatures. Non-volatile memory and temperature sensor applications exploiting temperature dependent hysteresis inversion and its reversibility in MoS 2 transistors have also been demonstrated. npj 2D Materials and Applications (2017) 1:34 ; doi:10.1038/s41699-017-0038-y INTRODUCTION Among two-dimensional materials, graphene 1,2 was the first to be isolated and studied with respect to electronic applications. Due to lack of an energy bandgap in graphene, other 2D materials such as layered transition metal dichalcogenides (TMDs) comprising a wide selection of materials with different bandstructures, and therefore different electrical and optical properties, have garnered significant attention.3-5 Molybdenum disulfide (MoS 2 ) has emerged as a prospective candidate for transistor applications. The presence of a direct bandgap (~1.8 eV) in monolayer form and an indirect bandgap (~1.2 eV) in multilayer MoS 2 makes it a promising channel material for field effect transistors (FETs).

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Section: Resultssupporting

confidence: 82%

Section: Resultsmentioning

confidence: 72%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Reversible hysteresis inversion in MoS2 field effect transistors

et al. 2017

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Pressure‐Tunable Ambipolar Conduction and Hysteresis in Thin Palladium Diselenide Field Effect Transistors

Bartolomeo

Pelella

Liu

et al. 2019

Adv Funct Materials

115

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Few-layer palladium diselenide (PdSe 2 ) field effect transistors are studied under external stimuli such as electrical and optical fields, electron irradiation, and gas pressure. The ambipolar conduction and hysteresis are observed in the transfer curves of the as-exfoliated and unprotected PdSe 2 material. The ambipolar conduction and its hysteretic behavior in the air and pure nitrogen environments are tuned. The prevailing p-type transport observed at atmospheric pressure is reversibly turned into a dominant n-type conduction by reducing the pressure, which can simultaneously suppress the hysteresis. The pressure control can be exploited to symmetrize and stabilize the transfer characteristics of the device as required in highperformance logic circuits. The transistors are affected by trap states with characteristic times in the order of minutes. The channel conductance, dramatically reduced by the electron irradiation during scanning electron microscope imaging, is restored after an annealing of several minutes at room temperature. The work paves the way toward the exploitation of PdSe 2 in electronic devices by providing an experiment-based and deep understanding of charge transport in PdSe 2 transistors subjected to electrical stress and other external agents.

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Dual‐Gated MoS₂ Memtransistor Crossbar Array

Lee

Sangwan

Rojas

et al. 2020

Adv Funct Materials

103

109

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Memristive systems offer biomimetic functions that are being actively explored for energy-efficient neuromorphic circuits. In addition to providing ultimate geometric scaling limits, 2D semiconductors enable unique gatetunable responses including the recent realization of hybrid memristor and transistor devices known as memtransistors. In particular, monolayer MoS 2 memtransistors exhibit nonvolatile memristive switching where the resistance of each state is modulated by a gate terminal. Here, further control over the memtransistor neuromorphic response through the introduction of a second gate terminal is gained. The resulting dual-gated memtransistors allow tunability over the learning rate for non-Hebbian training where the long-term potentiation and depression synaptic behavior is dictated by gate biases during the reading and writing processes. Furthermore, the electrostatic control provided by dual gates provides a compact solution to the sneak current problem in traditional memristor crossbar arrays. In this manner, dual gating facilitates the full utilization and integration of memtransistor functionality in highly scaled crossbar circuits. Furthermore, the tunability of long-term potentiation yields improved linearity and symmetry of weight update rules that are utilized in simulated artificial neural networks to achieve a 94% recognition rate of handwritten digits.

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Thermally Assisted Nonvolatile Memory in Monolayer MoS₂ Transistors

Cited by 53 publications

References 37 publications

Reversible hysteresis inversion in MoS2 field effect transistors

Reversible hysteresis inversion in MoS2 field effect transistors

Pressure‐Tunable Ambipolar Conduction and Hysteresis in Thin Palladium Diselenide Field Effect Transistors

Dual‐Gated MoS₂ Memtransistor Crossbar Array

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Thermally Assisted Nonvolatile Memory in Monolayer MoS2 Transistors

Cited by 53 publications

References 37 publications

Reversible hysteresis inversion in MoS2 field effect transistors

Reversible hysteresis inversion in MoS2 field effect transistors

Pressure‐Tunable Ambipolar Conduction and Hysteresis in Thin Palladium Diselenide Field Effect Transistors

Dual‐Gated MoS2 Memtransistor Crossbar Array

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Product

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Thermally Assisted Nonvolatile Memory in Monolayer MoS₂ Transistors

Dual‐Gated MoS₂ Memtransistor Crossbar Array