Through silicon via technology — processes and reliability for wafer-level 3D system integration

Ramm, Peter; Wolf, Marcus; Klumpp, Armin; Wieland, Robert; Wunderle, Bernhard; Michel, B.; Reichl, H.

doi:10.1109/ectc.2008.4550074

Cited by 94 publications

(25 citation statements)

References 1 publication

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“…Ghosh et al [17] have microscopically seen some slip bands appeared in Cu 3 Sn during the indention test, which indicates the question whether the IMC is really brittle or not is still debatable [18].…”

Section: Introductionmentioning

confidence: 99%

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Microstructural and mechanical analysis on Cu–Sn intermetallic micro-joints under isothermal condition

Chen

et al. 2015

Intermetallics

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Citation: MO, L. et al., 2015 Meanwhile, some equiaxial ultra-fine grains accompanied with the Kirkendall voids, were found only in adjacent to the electroplated copper. In addition, a specific type of micropillar with the size ~5μm×5μm×12μm fabricated by focus ion beam (FIB) was used to carry out the mechanical testing by Nano-indentation, which confirmed that this type of joint is mechanically robust, regardless of its porous Cu 3 Sn IMC interconnection.

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Section: Introductionmentioning

confidence: 99%

“…And, ensuring the reliability of these micro-joints (<10μm) has become one of the major challenges in the 3D integration [1][2][3]. Sn or Sn-based solder may be completely consumed with the scaling down size of joints during the stacking process, to form the entire intermetallic compounds (IMCs) interconnection.…”

Section: Introductionmentioning

confidence: 99%

Microstructural and mechanical analysis on Cu–Sn intermetallic micro-joints under isothermal condition

Chen

et al. 2015

Intermetallics

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“…to integrate SoC components, passives, but also ASICs, MEMS and RF devices (ITRS 2007). This concept is also called system-inpackage (SIP) (Reichl and Wolf 2006a;Reichl 2007;Ramm et al 2008a, b). An example is given in Fig.…”

Section: Introductionmentioning

confidence: 98%

Lifetime modelling for microsystems integration: from nano to systems

Wunderle

Michel

2009

Microsyst Technol

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Due to the rapid development of IC technology the traditional packaging concepts are making a transition into more complex system integration techniques in order to enable the constantly increasing demand for more functionality, performance, miniaturisation and lower cost. These new packaging concepts (as e.g. system in package, 3D integration, MEMS-devices) will have to combine smaller structures and layers made of new materials with even higher reliability. As these structures will more and more display nano-features, a coupled experimental and simulative approach has to account for this development to assure design for reliability in the future. A necessary ''nano-reliability'' approach as a scientific discipline has to encompass research on the properties and failure behaviour of materials and material interfaces under explicit consideration of their micro-and nano-structure and the effects hereby induced. It uses micro-and nano-analytical methods in simulation and experiment to consistently describe failure mechanisms over these length scales for more accurate and physically motivated lifetime prediction models. This paper deals with the thermo-mechanical reliability of microelectronic components and systems and methods to analyse and predict it. Various methods are presented to enable lifetime prediction on system, component and material level, the latter promoting the field of nano-reliability for future packaging challenges in advanced electronics system integration.

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“…In the current microelectronic package manufacturing, much complicated micro-joining technique, such as fine-pitch ball grid array (FBGA), chip scale packaging (CSP), and even through silicon via (TSV), are available or under active development [1][2][3]. Continuous development for newer technology may not substitute all the existing technology and moreover, for successful PCB assembly the role of SMT passives assembly cannot be neglected.…”

Section: Introductionmentioning

confidence: 99%

Process Optimization for Flexible Printed Circuit Board Assembly Manufacturing

Jeen¹,

Yeon²,

Seung-Soo³

2012

Transactions on Electrical and Electronic Materials

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A number of surface mount technology (SMT) process variables including land design are considered for minimizing tombstone defect in flexible printed circuit assembly in high volume manufacturing. As SMT chip components have been reduced over the past years with their weights in milligrams, the torque that once helped self-centering of chips, gears to tombstone defects. In this paper, we have investigated the correlation of the assembly process variables with respect to the tombstone defect by employing statistically designed experiment. After the statistical analysis is performed, we have setup hypotheses for the root causes of tombstone defect and derived main effects and interactions of the process parameters affecting the hypothesis. Based on the designed experiments, statistical analysis was performed to investigate significant process variable for the purpose of process control in flexible printed circuit manufacturing area. Finally, we provide beneficial suggestions for find-pitch PCB design, screen printing process, chip-mounting process, and reflow process to minimize the tombstone defects.

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Through silicon via technology — processes and reliability for wafer-level 3D system integration

Cited by 94 publications

References 1 publication

Microstructural and mechanical analysis on Cu–Sn intermetallic micro-joints under isothermal condition

Microstructural and mechanical analysis on Cu–Sn intermetallic micro-joints under isothermal condition

Lifetime modelling for microsystems integration: from nano to systems

Process Optimization for Flexible Printed Circuit Board Assembly Manufacturing

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