Tinkering with the well-tempered MOSFET: source–channel barrier modulation with high-permittivity dielectrics

Conventional spin transfer torque (STT) magnetoresistive random access memory (MRAM) generally includes a bulk n-channel MOS (NMOS) transistor as an access device that provides equal drive current in standalone conditions in both the directions. However, the switching current requirement of magnetic tunnel junctions (MTJs) in STT MRAM is highly asymmetric (2 to 3:1). With conventional access devices, the excess write current in one direction maps to unnecessarily higher power dissipation. Hence, in this paper, a novel STT MRAM cell with an asymmetric-dielectric (asymmetric-k) sidewall-spacer NMOS (ASNMOS) is presented. ASNMOS has different-k sidewall spacers, i.e., one side high-k and other side low-k spacer. As desired, this novel ASNMOS provides asymmetric drive current and reduces the overall power dissipation. The proposed STT MRAM cell is analyzed with HSPICE simulations using calibrated Verilog-A models for access device and perpendicular magnetic anisotropy MTJ. The STT MRAM cell with the proposed ASNMOS exhibits up to 25% reduction in the dynamic power dissipation over the STT MRAM cell with the conventional symmetric NMOS as an access device. Moreover, ASNMOS-based cells shows higher reliability wherein the worst case current density through MTJ is reduced by 25%. IndexTerms-Asymmetric-k sidewall-spacer NMOS (ASNMOS), HfO 2 spacer, magneto-resistive random access memory (MRAM), spin transfer torque (STT), write margin (WM).

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“…2. Similar improvement in drive current using high-k sidewall spacers has been verified in MOS-based devices in [9]- [11]. …”

Section: Architecture and Tcad Analysissupporting

confidence: 70%

Performance Enhancement of STT MRAM Using Asymmetric- Sidewall-Spacer NMOS

Verma

Pal

Mahawar³

et al. 2016

IEEE Trans. Electron Devices

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“…The performances of symmetric high-k devices are degraded due to high parasitic capacitances. Sachid et al [13] reported that the use of high-k spacers does not affect the barrier directly under the gate and hence the SCEs remain same as the conventional one. From circuit perspective, the delay depends on the relative rate of change of I ON and C gg [12].…”

Section: Electrostatics and Merits Of Asymd-k Finfetsmentioning

confidence: 99%

“…2(a) that the barrier directly under the channel is lowered to a lesser extent by the drain bias in AsymD-kS than conventional, hence the electrostatic integrity increases. In AsymD-kS structure, the increased source coupling competes with the gate to keep the channel potential near zero volts, illustrating how source-side injection governs the drain current in short device and reduces the effect of drain potential directly under the channel [13]. In other words, the gate voltage accumulates electrons (holes) in the n-type (p-type) device on the source side through the inner high-k spacer.…”

Section: Electrostatics and Merits Of Asymd-k Finfetsmentioning

confidence: 99%

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High-Performance and Robust SRAM Cell Based on Asymmetric Dual-$k$ Spacer FinFETs

Pal

Kaushik

Dasgupta

2013

IEEE Trans. Electron Devices

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This paper proposes a new asymmetric underlap Fin-Field Effect Transistor (FinFET) structure using a dual-k spacer. Asymmetric dual-spacer at source shows excellent gate control over the channel due to increase in the outer fringe field at gate/source underlap. Hence, this structure exhibits a superior short-channel effect metric over the conventional/single-spacer underlap FinFET. The proposed asymmetric structure enhances static random access memories (SRAMs) performance in terms of robustness, access times as well as leakage power during the hold, read, and write operations. The hold static noise margin and write margin increases by 5.16% and 5.66%, respectively. The read stability enhances by 13.75% and 19.35% over conventional FinFET SRAM circuit. Furthermore, the leakage power reduces by 60%, and write access time improves by 23.63%. Compared with conventional FinFET-based SRAM, same bit-cell area and read delay are associated with the proposed structure. Supply voltage scalability on SRAM design metrics is also investigated. In addition to SRAM application, underlap length, lateral source/drain doping gradient, and the high-k spacer width are optimized for high-performance digital applications.Index Terms-Access time, dual-spacer, low-power static random access memory (SRAM) cell, read static noise margin (SNM), robustness, underlap FinFET, write ability.

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