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PURPOSE PMOS transistor degradation due to Negative Bias Temperature Instability (NBTI) has been shown to be a major transistor reliability mechanism. The effect of PMOS NBTI on the minimum operating voltage of a cache cell (Vmin) has been recently demonstrated [I J, and the modeling of the degradation of ultra small gate area devices is vital for the accurate modeling of Vmin. Recent data and simulation has indicated that random fluctuations in device degradation are present under stress. This paper examines the source of these random fluctuations in device degradation due to PMOS NBTI.PMOS NBTI transistor degradation is an important reliability mechanism and has been shown to be one of the major limiters for product lifetime [2,3].PMOS N3TI effects originate from the formation of fixed oxide charge and the creation of interface states. These effects manifest themselves as shifts in threshold voltage and transconductance, For large gate area devices, these shifts can cause failure of digital circuits to meet timing windows or can create undesirable mismatch in analog circuits.Recent observations on PMOS devices with small gate areas show that the degradation of both drain current and threshold voltage appear to be subject to random fluctuations.These fluctuations increase a5 a function of stress time and are affected by the current density. It is believed that the additional instability is due a discrete random trapped charge effect, similar to what has been recently observed for discrete-trap memories [4]. The trapped charge can occur at random locations across the gate and can affect the drain current de-pending on the local current density. This paper examines the effects of PMOS NBTI-induced random fluctuations on device degradation. It clearly demonstrates that this geometric effect is due to the statistical nature of random trapped charge in the oxide and the effect of this charge on the percolation path through the channel of a small gate area device. MODELINGThe statistical nature of the random charge effect can be modeled in a similar fashion as has been done for random dopants. Charges placed at discrete points in the channel region can constrict the current flow in a small gate area devices by locally modifylng the threshold voltage. As illustrated in Figure 1, if random charges are placed at discrete points along a conducting path from source to drain, the current flow will be forced to areas of lower threshold voltage and could possibly be shut off entirely. CHANKEL FIGURE 1: ILLUSTRATION OF CURRENT FLOW FROM SOURCE TO DRAW IN A SMALL GATE AREA DEVICE. OPEN CIRCLE REPRESENT FILLED TRAPS THAT ALTER THE CURRENT FLOW FROM SOURCE TO DRAIN. Keyes [5] derived a relationship expressing the fluctuation in the threshold voltage as a function of channel doping and gate area. In this derivation, the probability of a conducting path from source to drain is determined by the local probability of a given area in the channel having a number of impurities less than a critical threshold, m,. This probability can be...

contact (BEC) and GST phase change layers (Fig 2). This Phase change memory (PCM) research has largely focused on approach self-aligns BEC and GST regions reliably to bulk properties to evaluate cell efficiency. Now both produce an efficient PCM cell. electrical and thermal interface resistances are characterized and shown to be critical for understanding power in a novel Damascene-GST cell. Interfaces reduce reset power 20% and reset current 40% and allow reset current to scale faster than it would without interfaces.

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