Valence-band tunneling enhanced hot carrier degradation in ultrathin oxide nMOSFETs

Abstract

Enhanced hot camer degradation with stress V, in the valence-band tunneling regime is observed. This degradation is attributed to channel hole creation by valence-band electron tunneling. The created holes provide for Auger recombination with electrons in the channel and thus increase hot electron energy. The valence-band tunneling enhanced hot carrier degradation becomes more serious as gate oxide thickness is reduced. In ultra-thin gate oxide nMOSFETs, our result shows that the valence-band tunneling enhanced degradation, as opposed to max. Ib stress induced degradation, exhibits positive dependence on substrate bias. This phenomenon may cause a severe reliability issue in positively biased substrate or floating substrate devices.

Auger recombination-enhanced hot carrier degradation in nMOSFETs with a forward substrate bias

“…In ultrathin oxide nMOSFETs [ Fig. 1(b)], a positive gate bias can cause valence-band electron direct tunneling to the gate and leave a hole behind in the channel for Auger process [8], [9]. In Fig.…”

Some issues of hot-carrier degradation and negative bias temperature instability of advanced SOI CMOS transistors

“…Another reason also suggesting worse degradation for the FB devices is the channel electron energy redistribution through valence-band electron direct tunneling into the gate [7]. The inset in Fig.…”

“…These include impact ionization feedback [6], valence-band tunneling [7] and thermally assisted impact ionization [8]. It must be noted here that thermally assisted processes are particularly important for SOI devices, as they are more likely than bulk devices to operate at elevated temperatures due to the self-heating effect (SHE).…”

Excess Low-Frequency Noise in Ultrathin Oxide n-MOSFETs Arising From Valence-Band Electron Tunneling

“…Furthermore, significant substrate current arises in the 15-oxide device in strong inversion regime V in Fig. 3 because valence-band electron tunneling from the Si substrate to the polysilicon gate occurs and generated holes flow to the substrate [16]. decreases and increases because of a larger channel electron population and thus a smaller electron capture time.…”