Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications

Pal, Soumitra; Islam, Aminul

doi:10.1109/tcad.2015.2474408

Cited by 120 publications

(47 citation statements)

References 34 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A 6T-Decoupled SRAM Cell has been proposed in [7] which works good for low voltage and half select column also. 8T SRAM in [8] proposed for low power and improved stability. In [9] for enhanced stability SRAM using FinFET with dynamic gate voltage adjustment has been proposed SRAM cell with pass gate feedback has been proposed in [10].…”

Section: B Sram Cellsmentioning

confidence: 99%

FinFET SRAM cell with improved stability and power for low power applications.

Birla

2019

JICS

View full text Add to dashboard Cite

In this paper, a new 11T SRAM cell using Double gate FET (FinFET technology) has been proposed, cell basic component is the 6T SRAM cell with 4 NMOS access transistors to improve the stability over CMOSFET circuits and also makes it a dual port memory cell. The proposed cell also used a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability which helps in reducing the leakage current, active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at threshold and subthreshold voltage 2.68x with D6T SRAM cell, 5.5x with TG8T. The WSNM (Write Static Noise Margin) and HM (Hold Margin) of the SRAM cell at 0.9V is 306mV and 384mV.At subthreshold operation also, it shows improvement. The Leakage power reduced by 0.125x with LP8T, 0.022x with D6T SRAM cell, TG8T and SE8T. Impact of process variation on cell stability also been analyzed.

show abstract

Section: B Sram Cellsmentioning

confidence: 99%

FinFET SRAM cell with improved stability and power for low power applications.

Birla

2019

JICS

View full text Add to dashboard Cite

show abstract

“…The bitlines are connected to the sense amplifier (not shown here). The output of the sense amplifier provides information about the stored [23][24][25] data by recognising the voltages at two bitlines (BL and BLB). The variations of these bitline voltages are shown in Fig.…”

Section: Read Operationmentioning

confidence: 99%

Design and development of memristor‐based RRAM

Pal

Gupta

et al. 2019

IET Circuits, Devices & Systems

Self Cite

View full text Add to dashboard Cite

A power-and variability-aware non-volatile resistive random access memory (RRAM) cell is presented. Non-volatility is achieved due to the use of a memristor as a memory element, which when integrated with a carbon nanotube field-effect transistor (CNFET) helps achieve tremendous robustness against process variation. The half-select issue, inherent in the 2T2M RRAM cell (state-of-the-art design based on the memristor) have been resolved and its circuit parameters have been compared with those of the proposed cell. Also, the proposed cell has been compared with the standard 6T SRAM (S6T) cell. The proposed cell shows 1.6×/4.08× narrower read delay/write delay variability compared with 2T2M. 5CNFET2M also shows 1.8× narrower read delay variability than that of S6T. Furthermore, the proposed cell shows 6.9× shorter write delay in comparison with the 2T2M RRAM cell. 5CNFET2M consumes 10 6 ×/1.34× lower power during hold mode compared with the conventional 6T static random access memory/2T2M RRAM cell. Furthermore, the proposed cell also shows improvement in hold power variability compared with both the cells. All the simulated data, presented here are at the nominal supply voltage of 1 V. These improvements are gained at the expense of slightly longer read time compared with 2T2M/S6T and 31.3× longer write delay compared with S6T.

show abstract

“…The noise generated from threshold variation, process variation, half select issue and multiple bit errors, reduces the stability of SRAM cell. Consequently, various techniques have been employed to overcome those limitations, such as scaling the supply voltage using process variation tolerant Schmitt trigger based ST10T SRAM [39], a read static noise margin free 7T SRAM [40], differential data aware power supplied D2AP8T SRAM [41], low leakage variation tolerant LP8T [42], LP9T [43] and LP10T SRAM [44] for ULP applications. Besides the advantages provided by these cells, there are some limitations like read stability, consequences of temperature variations in leakage power, low WTP and higher power delay product (PDP) in subthreshold regime.…”

Section: Related Work and Motivationmentioning

confidence: 99%

Ultra Low Power Process Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Singh¹,

Vishvakarma²

2017

Preprint

View full text Add to dashboard Cite

An ultra-low power (ULP), power gated static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates in sub-threshold voltage ranges from 300mV to 500mV. The proposed SRAM has tendency to operate in low supply voltages with high static and dynamic noise margins. The IoT application involves battery enabled low leakage memory architecture in subthreshold regime which has low power consumption. Therefore, to improve power consumption along with better cell stability, a power gated 10T SRAM is presented. The proposed cell uses a power gated p-MOS transistor to reduce the leakage power or static power in standby mode. Moreover, due to the schmitt triggering and read decoupling of 10T SRAM the static and dynamic behavior in read, write and standby mode has shown enhanced tolerance at different process, voltage and temperature (PVT) conditions. The proposed SRAM shows better results in terms of leakage power, read static noise margin (RSNM), write static noise margin (WSNM), write-ability or write trip point (WTP), read-write energy and dynamic read margin (DRM). Further, these parameters are observed at 8-Kilo bit (Kb) and compared with already existing SRAM architectures. It is observed that the leakage power is reduced by 1/81×, 1/75× of the conventional 6T (C6T) SRAM and read decoupled 8T (RD8T) SRAM, respectively at 300mV VDD. On the contrary, RSNM, WSNM, WTP and DRM values are improved by 3×, 2×, 11.11% and 31.8% as compared to C6T SRAM, respectively. Similarly, proposed 10T has 1.48×, 25% and 9.75% better RSNM, WSNM and WTP values as compared to RD8T SRAM, respectively at 300mV VDD.Keywords: power gating; read decoupling; read-write static noise margin; dynamic noise margin; read-write energy; schmitt trigger; leakage power. IntroductionThe massive constrain headed for internet of things (IoT) devices has led to developments of ultra-low power (ULP) systemson-chip (SoCs) that are capable of operating in sub-threshold voltages [1,2]. One way to guarantee low power and energy consumption is to scale down the supply voltage to the sub-threshold region [3]. However, the reduced on-to-off current ratio (I ON /I OFF ) and the exponential dependence of the current on the threshold voltage (V th ) in the sub-threshold region introduces many challenges especially in rationed circuits such as the traditional 6T static random access memory (SRAM) bit-cell. Since, conventional non-volatile memories consume higher read and write power, the scaling of supply voltages and the techniques to reduce leakage at sub-threshold voltages needed. However, the low cell stability is also one of the factor which defy conventional SRAM architecture to not to work at sub-threshold region [4].However, due to rapid growth of internet market through all over the world, Internet of Things (IoT) brings connectivity, communication, and data gathering to existing devices. IoT includes countless devices connected and communicated with each other to enrich the present lifestyle, and its applicabi...

show abstract

Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications

Cited by 120 publications

References 34 publications

FinFET SRAM cell with improved stability and power for low power applications.

FinFET SRAM cell with improved stability and power for low power applications.

Design and development of memristor‐based RRAM

Ultra Low Power Process Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Contact Info

Product

Resources

About