vfTLP-VTH: A new method for quantifying the effectiveness of ESD protection for the CDM classification test

Zhou, Yuanzhong; Ellis, David F.; Hajjar, Jean-Jacques; Olney, Andrew; Liou, Juin J.

doi:10.1016/j.microrel.2012.04.011

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Vftlp-vt Testing Configuration1

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Cited by 3 publications

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“…The standard VFTLP has been extended to a new evaluation methodology, known as VFTLP-VT [4,5]. In a VFTLP-VT configuration, a gate-oxide monitor element is included in parallel with the ESD protection device (Figure 1).…”

Section: Vftlp-vt Testing Configurationmentioning

confidence: 99%

Investigation on effectiveness of series gate resistor in CDM ESD protection designs

Zhou

Righter

Hajjar

2013

2013 IEEE 10th International Conference on ASIC

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The impact of gate series resistor on CDM protection effectiveness is systematically evaluated using SPICE simulation and verified with a modified VF-TLP test method. It is shown that the effectiveness of the resistor to a MOS input device is highly dependent on the size of the protected MOS device as well as on the types of ESD protection circuits. Larger MOS devices require smaller resistance values than smaller devices.

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Section: Vftlp-vt Testing Configurationmentioning

confidence: 99%