In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography to pattern the first interconnect level (metal 1).This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip (product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity of 3.8 mJ/cm 2 , providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as evidenced by electrical test results.Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.

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Single exposure lithography is the most cost effective means of achieving critical level exposures, and extreme ultraviolet lithography (EUVL) is the technology that will enable this for 27nm production and below. ASML is actively engaged in the development of a multi generation production EUVL system platform that builds on TWINSCAN™ technology and the designs and experience gained from the build, maintenance, and use of the Alpha Demo Tools (ADTs). The ADTs are full field step-and-scan exposure systems for EUVL and are being used at two research centers for EUVL process development by more than 10 of the major semiconductor chip makers, along with all major suppliers of masks and resist. In this paper, we will present our EUVL roadmap, and the manufacturing status of the projection lens for our first production system. Included will also be some test data on the new reticle pods. Experimental results from ADT showing the progress in imaging (28 nm half pitch 1:1 lines/spaces CDU ~10%), single machine overlay down to 3 nm, and resist complete the paper.