One of the popular design methodologies for power distribution networks (PDNs) is to identify a target impedance to be met across a broad frequency range. The methodology is based on the assumption that the ratio of the timedomain maximum output voltage noise to the multiplication of target impedance and time-domain maximum input current is no more than one. In this paper, the ratios for different impedance profiles are analyzed, and the assumption is proved to be not necessarily true. Particularly, for secondorder impedances, the maximum ratio can be two. Several cases with real PDN structures are investigated to support our analysis. A real case of the complete PDN path with the ratio of 1.585 is given.

C05-177, (stevenyun.jiintellcom) Steve Peterson, FM7-287, steven.peterson@intel.com) Jian-Liang Chen, C05-177, (/ian-1iang.chen@intel,com) Christopher Pan, C05-1577,,herpanintel.com ABSTRACT I/O power represents a sizeable portion of the overall power budget on a low power mobile platform. Significant fraction of that I/O power is used to ensure signal integrity on the high speed buses. While there is flexibility to trade off I/O power consumption against signal quality on Intel's current mobile and sub-note platforms, inefficiency still exists on wide I/O buses such as FSB and DDR2. In this paper, we will outline two novel bus termination schemes that can significantly reduce FSB and DDR2 I/O power consumption by further trading off signal quality on the new Low Power IA (LPIA) Ultra Small PC (UMPC) platforms.

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The impact of power integrity on processor performance is critical in nano-scale era. We proposed the enhanced pre-silicon simulation to accurately capture the power delivery quality. The post silicon performance measurements correlates well with pre-silicon analysis and demonstrate that power integrity could impact performance up to 15% in low and high frequencies.