Sub-resolution assist features (SRAF) have been shown to provide significant process window enhancement and across chip line-width variation reduction when used in conjunction with modified illumination lithography. Work previously presented at this conference has focused on the optimization of sraf design rules that specify the predominantly one dimensional placement and width of assist features as a function of layout pitch. This paper will recount the optimization of SRAF style options that specify how SRAF are to behave in realistic two dimensional circuit layouts. Based on the work done to strike the correct balance between sraf manufacturability, CAD turnaround time, and lithographic benefit in IBM's early product implementation exercises, the evolution of sraf style options is presented. Using simulation as well as exposure data, this paper explores the effect of various two dimensional sraf layout solutions and demonstrates the use of model based verification in the optimization of sraf style options.

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A special technique to electrically measure submicrometer isolated features is described. By incorporating a large number of features in a single test structure, a gain in precision better than 3 nm can be achieved. The interpreted contact hole diameter as well as the area of the isolated features were found to be very accurate. The special test pattern, an analytic expression for interpretation of the results, and hole size data from a variety of exposure dosages are included. ABSTRACTA special technique to electrically measure submicrometer isolated features is described. By incorporating a large number of features in a single test structure, a gain in precision better than 3 nm can be achieved. The interpreted contact hole diameter as well as the area of the isolated features were found to be very accurate. The special test pattern, an analytic expression for interpretation of the results, and hole size data from a variety of exposure dosages are included.