The increase in sheet resistance of indium–tin–oxide (ITO) films on polyethylene terephthalate with increasing tensile strain is reported. The increase in resistance is related to the number of cracks in the conducting layer which depends upon applied strain and film thickness. We propose a simple model that describes the finite but increasing resistance in the cracked ITO layer in terms of a small volume of conducting material within each crack.

Agglomeration process in thin silicon-, strained silicon-, and silicon germanium-on-insulator substratesThe thermal agglomeration of ultrathin ͑Ͻ30 nm͒ single crystal silicon-on-insulator ͑SOI͒ films is a morphological evolution phenomenon with practical and scientific importance. This materials phenomenon represents both a critical process limitation for the fabrication of advanced ultrathin SOI-based semiconductor devices as well as a scientifically interesting morphological evolution problem. Investigations to date have attributed this phenomenon to a stress-induced morphological instability. In this paper, we demonstrate that SOI agglomeration is a surface-energy-driven dewetting phenomenon. Specifically, we propose that agglomeration occurs via a two-step surface-energy-driven mechanism consisting of ͑1͒ defect-mediated film void nucleation and ͑2͒ surface-diffusion-limited film dewetting via capillary edge and generalized Rayleigh instabilities. We show that this theory can explain all of the key experimental observations from the SOI agglomeration literature, including the locations of agglomeration initiation, the greater instability of patterned film edges, the destabilizing effect of decreasing silicon layer thickness and increasing temperature, the strikingly periodic silicon finger and island formation agglomeration morphology, and the scaling of agglomerated structure dimensions with the silicon layer thickness. General implications of this theory for the thermal stability of SOI and other common thin-film-on-insulator structures are also discussed.

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Multilevel thin film processing, global planarization and advanced photolithography enables the ability to integrate complimentary materials and process sequences required for high index contrast photonic components all within a single CMOS process flow. Developing high performance photonic components that can be integrated with electronic circuits at a high level of functionality in silicon CMOS is one of the basic objectives of the EPIC program sponsored by the Microsystems Technology Office (MTO) of DARPA. Our research team consisting of members from: BAE Systems, Alcatel-Lucent, Massachusetts Institute of Technology, Cornell University and Applied Wave Research reports on the latest developments of the technology to fabricate an application specific, electronic-photonic integrated circuit (AS_EPIC). Now in its second phase of the EPIC program, the team has designed, developed and integrated fourth order optical tunable filters, both silicon ring resonator and germanium electro-absorption modulators and germanium pin diode photodetectors using silicon waveguides within a full 150nm CMOS process flow for a broadband RF channelizer application. This presentation will review the latest advances of the passive and active photonic devices developed and the processes used for monolithic integration with CMOS processing. Examples include multilevel waveguides for optical interconnect and germanium epitaxy for active photonic devices such as p-i-n photodiodes and modulators.