High-resolution Sigma-Delta (ΣΔ) ADCs are increasingly used in portable medical applications for the measurement of biopotential signals. This paper presents the implementation and measurements of a novel ultra-low power low voltage multi-bit continuous-time sigma-delta (CT-ΣΔ) modulator, whose quantizer and feedback DACs operate in the time domain. Instead of the conventional flash quantizer and mismatch corrected multi-bit feedback DACs, a Dual-Slope (DS) quantizer and a Pulse-Width Modulated (PWM) DACs have been adopted in this design. The modulator has been implemented in a standard 0.18μm CMOS technology and features 83dB dynamic-range (DR) for a signal bandwidth of 256Hz. When clocked at 917kHz it consumes 13.3μW from a 1.4V supply.

The ADC shown in this paper uses an innovative Sigma-Delta (61) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-61 ADC prototype has been fabricated in 0.13 m CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = Pwr 2 BW 2 ENOB ) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm 2 .

This paper presents the system level design of a novel multi-bit Sigma-Delta (ΣΔ) ADC architecture that replaces the flash quantizer and mismatch corrected multi-bit DAC of a ΣΔ modulator by an integrating quantizer and a Pulse-Width Modulated DAC. This converter achieves the resolution of a multi-bit design using single-bit circuitry. The quantizer of this modulator is similar to a classical Dual-Slope integrating converter, but the charge residue in the integrator at the end of each conversion cycle is stored for the next conversion, providing first order noise shaping. As an example, the system level performance of a second-order multi-bit ΣΔ ADC using this new architecture has been evaluated. Also, circuit level specifications have been established, considering the most critical circuit non-idealities. The behavioral simulation results show that the ADC could achieve an ENOB = 13bits in a signal bandwidth of 2 MHz using conventional CMOS technology, which could be suitable for wireless communication standards.

A novel multibit continuous time sigma-delta modulator architecture that does not require a flash converter is presented. The quantiser of this modulator is similar to an integrating ADC that is operated with a binary weighted charge balancing algorithm. The charge residue in the integrating ADC at the end of each conversion cycle is accumulated for the next conversion, providing first-order noise shaping. The modulator order can be increased by the addition of more integrating stages.Continuous time sigma-delta (CTSD) modulators are nowadays a successful solution for data conversion, implemented in most cases as multibit designs [1]. New nanometre technologies challenge multibit modulators, especially in the design of their internal flash converter, owing to the low supply voltage and limited performance of the analogue blocks [2]. In this Letter we present a new architecture that implements a multibit CTSD modulator without requiring a flash converter, yet keeping similar operational amplifier requirements than standard multibit modulators.Some previous works [3,4] have shown oversampling converters that use the successive approximations principle. The quantiser of the modulator discussed in this Letter is similar to an integrating ADC where the charge stored in the integration phase is afterwards measured with a successive approximations algorithm. The charge residue present at the integrator after a measurement cycle is stored for the next conversion, providing first-order noise shaping. As a difference, the SAR ADC in [3] is used only as a quantiser and is not embedded in the loop filter. On the other hand, the converter in [4] requires switched capacitor circuits, the linearity of which may be affected by a low supply voltage. However, the proposed solution is based on continuous time integrators and may use current-mode DACs and switches, which are suitable for low supply voltages. The modulator order can be increased by the addition of more integrating stages, making this architecture a power and area efficient solution for converters of low or medium speeds.Fig. 1 Building block diagram and equivalent modulatorFirst-order multibit modulator: The system depicted as 'block A' in Fig. 1a represents a multibit first-order sigma-delta modulator which will be used as a basic building block. It is composed of a switch SW, a continuous time integrator with gain K, a comparator, an N bit DAC and a state machine as digital controller. Let T s be the desired sampling period of the modulator. The clock period of the digital controller will be T clk ¼ T s /(N þ M), where N is the desired quantiser resolution and M is another integer which defines the integration period. The operation of block A during the nth conversion period is depicted in Fig. 2 and is divided into two phases named I and II, which will last M and NT clk clock cycles, respectively. During phase I, the digital controller will connect the integrator to input I of SW. We will define the auxiliary signal V x (t) as:The value of V c (t) in Fig. 1 at t ¼...