Devices and interconnect structures of new semiconductor and packaging technologies show parasitic physical effects with a growing influences of the system behavior. Therefore, the design technology has to be developed and adjusted to ensure high system performance and reliability of these very complex systems on chip and in a stack. The influences of parasitic effects on the circuit behavior have to be minimized within the design process.Typical parasitic effects of the Vertical System Integration (VSI ® ) by stacked silicon are discussed in this paper. Effects like electro thermal coupling, electromagnetic interactions, and the sensitivity due to parameter variations and their influence to the system behavior are identified and modeled. Approaches for minimization of these influences by design modifications are presented.Keywords stacked silicon, 3D integration, vertical system integration, design for manufacturability, robust design, modeling Mater. Res. Soc. Symp. Proc. Vol. 970

Functional aspects as well as the influence of integration technology on the system behavior have to be considered in the 3D integration design process of micro systems. Therefore, information from different physical domains has to be provided to designers. Due to the variety of structures and effects of different physical domains, efficient modeling approaches and simulation algorithms have to be combined. The article describes a modular approach which covers detailed analysis with PDE solvers and model generation for system level simulation

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