The transport of B atoms out of p+ polycrystalline silicon (poly-Si) gate electrodes through SiO2 gate oxides to the Si–SiO2 interface during dopant activation anneals degrades performance and reliability of hole-conducting (p-channel) field effect transistors. This article studies the suppression of B atom transport by using remote plasma processing to form ultrathin Si3N4 and silicon oxynitride diffusion barrier layers between p+ poly-Si gate electrodes and SiO2 gate dielectrics. Suppression of B atom transport has been monitored through electrical measurements, demonstrating that ∼0.8 nm of Si3N4, equivalent to a N areal density of ∼4.5×1015 atoms cm−2, is sufficient to effectively suppress B out diffusion during aggressive anneals of ∼1 min at 1000 °C. The suppression and transport mechanisms in nitrides, oxides, and oxynitrides have been studied by varying the N atom areal density by alloying. Quantum chemistry calculations suggest that B transport occurs through the formation of donor-acceptor pair bonds between B+ ions and nonbonding electron pairs on oxygen atoms with the transport process requiring a connected O atom percolation pathway. Donor-acceptor pair bonds with B+ ions are also formed with N atoms in nitrides and oxynitride alloys, but with a binding energy more than 1.5 eV higher than B+ ion O-atom bonds so that nitrides and oxynitride alloys effectively block B diffusion through the formation of a deep trapping site.

Band alignment of TiN/HfO2 interface of TiN/HfO2/SiO2/Si stack is investigated by x-ray photoelectron spectroscopy (XPS). The p-type Schottky barrier height (p-SBH) is found to increase with thicker HfO2 thickness. Since considering only the metal/dielectric interface cannot explain this phenomenon, band alignment of TiN/HfO2 interface of TiN/HfO2/SiO2/Si stack is demonstrated based on band alignment of entire gate stack. Dependence of p-SBH on HfO2 thickness is interpreted and contributed to fixed charges in gate stack, interfacial gap state charges at HfO2/SiO2 interface, and space charges in Si substrate. Electrical measurements of capacitor structures further support XPS results and corresponding explanation.

We studied the effect of selective oxidation conditions on gate oxide characteristics. Selective oxidation in hydrogen-rich wet ambient at 850°C–950°C was found to generate defects both at the SiO2/Si interface and in oxide bulk, resulting in a higher stress-induced leakage current. The degradation of the device can be explained by the incorporation of hydrogen into the gate oxide during a high-temperature selective oxidation process. The plasma reoxidation process induced fewer defects due to radical oxidation at low temperature.

We investigated the effect of post-thermal processing on the gate oxide reliability in nitride/W/WNx/polycrystalline-Si (poly-Si) gated metal-oxide-semiconductor (MOS) capacitors. As the thermal processing became severer, grater development of mechanical stress and degradation of the gate oxide were observed. Microvoids were also found at the triple point between the gate oxide and two poly-Si grains. The wide variation in mechanical stress during post-thermal processing is believed to create the microvoids and generate additional dangling and strained bonds in the oxide and at the SiO2/Si interface, resulting in the degradation of the gate oxide.

No abstract