Abstract-Self-assembled monolayers (SAMs) of either ferrocenecarboxylic acid or 5-(4-Carboxyphenyl)-10,15,20-triphenylporphyrin-Co(II) (CoP) with a high-κ dielectric were integrated into the Flash memory gate stack. The molecular reductionoxidation (redox) states are used as charge storage nodes to reduce charging energy and memory window variations. Through the program/erase operations over tunneling barriers, the device structure also provides a unique capability to measure the redox energy without strong orbital hybridization of metal electrodes in direct contact. Asymmetric charge injection behavior was observed, which can be attributed to the Fermi-level pinning between the molecules and the high-κ dielectric. With increasing redox molecule density in the SAM, the memory window exhibits a saturation trend. Three programmable molecular orbital states, i.e., CoP 0 , CoP 1− , and CoP 2− , can be experimentally observed through a charge-based nonvolatile memory structure at room temperature. The electrostatics is determined by the alignment between the highest occupied or the lowest unoccupied molecular orbital (HOMO or LUMO, respectively) energy levels and the charge neutrality level of the surrounding dielectric. Engineering the HOMO-LUMO gap with different redox molecules can potentially realize a multibit memory cell with less variation. Index Terms-Coulomb blockade effect, high-κ dielectric, nonvolatile memory devices, reduction-oxidation (redox)-active molecules, self-assembled monolayer (SAM).

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Below the 65-nm technology node, scaling of Flash memory, NAND, NOR or embedded, needs smart and heterogeneous integration of materials in the entire device structure. In addition to maintaining retention, in the order of importance, we need to continuously make functional density (bits/cm2) higher, cycling endurance longer, program/erase (P/E) voltage lower (negated by the read disturbance, multi-level possibility and noise margin), and P/E time faster (helped by inserting SRAM buffer at system interface). From both theory and experiments, we will compare the advantages and disadvantages in various material choices in view of 3D electrostatics, quantum transport and CMOS process compatibility.

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