No abstract

Due to the high process temperature required for fusion bonding (e.g. ~1000°C) this process was not attractive for 3D applications. In the recent years low temperature fusion bonding processes were developed for addressing low temperature applications. A low temperature CMOS compatible fusion bonding process based on plasma activation of the substrate surfaces prior bonding was developed. The low temperature fusion bonding process was used in combination with standard thin wafer manufacturing processes in order to enable and demonstrate thin layer wafer bonding with subsequent multi-layer stacking capability. The process is compatible with the high cleanliness levels required by CMOS technology and can be used for various application scenarios involving through-silicon vias (TSV) technology.

The goal of the presented work is to study the delamination root cause in temporary bonding using thermoplastic material as adhesive. The parameters potentially involved in this mechanism are defined, and each of them is separately studied. At the end, the combination between some of the parameters is also tested. Finally the mechanism at the root of the delamination is discussed.

The high process temperature required for silicon oxide fusion bonding (e.g. ~1000°C) prevented its use for 3D applications. In the recent years low-temperature fusion bonding processes (200°C – 400°C) have been developed for addressing such applications. In this study, low-temperature fusion bonding in combination with standard thin wafer manufacturing processes based on temporary bonding/debonding technology in order to demonstrate thin layer direct bonding with subsequent multi-layer stacking capability using standard semiconductor manufacturing bonding equipment. Monolithic integration of two 10µm thin temporary bonded silicon layers onto a standard 775µm thick Si wafer is shown and discussed in detail.

As 3D-TSV technology based solutions are moving into volume manufacturing, monitoring of the processed device wafer through temporary bonding, thinning, TSV reveal, metallization and de-bonding processes remains a key yield concern. Edge chipping, micro-cracks, device-carrier misalignment, adhesive residue at edge and delamination during device wafer thinning and later process steps are some of the process challenges. Monitoring of device wafer edge for bond process defects and device-carrier concentricity is critical to ramp-up yields and reduce the overall cost of ownership of the TSV process flow. Additionally, to get the highest yield from temporary bonding process, thickness and TTV (total thickness variation) measurements from different layers of the bonded stack as well as detecting bonding voids in one single measurement run is vital.In this contribution, we will discuss the main factors affecting edge yield of temporary bonded and thinned device wafers and demonstrate the use of automated edge inspection and metrology for process control and yield improvement.