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In this paper, the effect of SiN pull-back process for shallow trench isolation (STI) is investigated by measuring DRAM array's refresh time (Tref) and yield as sensitive monitors. The SiN pull-back is performed by using H3P04 solution after trench etch (i.e. before liner oxidation). For comparison, DRAMS were fabricated by using various isolation methods including LOCOS, conventional STI, and poly-buffered STI (PB-STI). The SiN pull-back process is known for reducing "divot" around the top corner in conventional STI. Both LOCOS and PB-STI can result in "divot" free. It is also known that 'Ldivot" will degrade the inverse narrow width effect of pass transistor and result in "double hump". In our study, SiN pull-back in STI indeed eliminates "double-hump'' in Id-vg curves of pass transistors. The SiN pull-back also can result in better data retention of DRAM than if without pull-back, but comparable to LOCOS and PB-STI. The optimized window of SiN pull-back in this study is 1 Onm to 40 nm with best yield at 15nm (slightly better yield than LOCOS and PB-STI).

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This paper reports a metal-oxide RRAM with novel Defect Engineering Technology (DET) that achieves forming-free, multi-level capable, self-rectifying, large 2x10 4 resistance window, ultra-low 0.24nW reset power and good endurance of 10 6 cycles at the same time. Besides, by the same DET with additional forming process, we demonstrate a complementary resistive switching (CRS) on singlestack metal-oxide with large 15X resistance window, good endurance of 10 5 cycles and stable high-temperature disturbance.