A robust shallow trench isolation (STI) with SiN pull-back process for advanced DRAM technology

Abstract

In this paper, the effect of SiN pull-back process for shallow trench isolation (STI) is investigated by measuring DRAM array's refresh time (Tref) and yield as sensitive monitors. The SiN pull-back is performed by using H3P04 solution after trench etch (i.e. before liner oxidation). For comparison, DRAMS were fabricated by using various isolation methods including LOCOS, conventional STI, and poly-buffered STI (PB-STI). The SiN pull-back process is known for reducing "divot" around the top corner in conventional STI. Both LOCOS and PB-STI can result in "divot" free. It is also known that 'Ldivot" will degrade the inverse narrow width effect of pass transistor and result in "double hump". In our study, SiN pull-back in STI indeed eliminates "double-hump'' in Id-vg curves of pass transistors. The SiN pull-back also can result in better data retention of DRAM than if without pull-back, but comparable to LOCOS and PB-STI. The optimized window of SiN pull-back in this study is 1 Onm to 40 nm with best yield at 15nm (slightly better yield than LOCOS and PB-STI).

A Robust Shallow Trench Isolation High Density Plasma Chemical Vapor Deposition Void Free Process for 0.13μm CMOS Technology

“…Shallow Trench Isolation(STI) is a device isolation technique for integrated circuits. As the semiconductor industry moved to sub 0.25um CMOS technology there is a need for creating very small void free gaps on the wafer sub-layer [1,2,3,4] . STI is a mainstream isolation method for advanced logic, DRAM, SRAM and flash memory.…”

Novel STI scheme and layout design to suppress the kink effect in LDMOS transistors

“…These can result in the inverse narrow width effect (INWE), gate oxide integrity (GOI) degradation, extra subthreshold leakage and power dissipation. Among the recent reports on the suppression of subthreshold kinks [4][5][6][7][8], large tilted sidewall boron implantation [4] seems to be easily manufacturable. However, this process involves extra lithography to avoid the impact on the p-channel MOS region.…”

“…Kim et al have reported using a nitric oxideannealed sidewall to suppress boron out diffusion [5], but simultaneously introduce latent GOI risk due to the slow oxidation rate on the nitrided silicon surface. Although other methods based on active corner engineering [6][7][8] show an improved performance, they all seem to have a downscaling limitation, because in the liner oxidation step the active width of narrow devices cannot be well controlled. Although the kink effect has been widely investigated and effectively eliminated in standard CMOSFETs, the subthreshold characteristics of LDMOSFETs have not been well studied.…”