No abstract

No abstract

We have developed a new high-performance ion source on the basis of the high-density plasma formation method known as magnetically neutral loop discharge (NLD). The ion source consists of three separate electromagnetic coils, an ion extraction electrode, and a quartz vessel plasma chamber with a one-turn RF antenna coil, which is the main component of conventional RF ion sources. The three electromagnetic coils are located around the periphery of the plasma chamber. The current in the middle coil flows opposite to the currents in the top and bottom coils. With this configuration, our source produces a high plasma density of 10 11 cm À3 , which is about ten times higher than that of a conventional source under a low gas pressure of 0.1 Pa. In addition, it is possible to control both the ring like plasma diameter and the high-density plasma generation position in the plasma chamber. As a result, we achieved a high ion current density of up to 1 mA/cm 2 at 50 V of ion extraction voltage, which is almost five times higher than the conventional source. Furthermore, we also obtained a high ion current uniformity of AE5% over a 6-in.-diameter wafer using the source's plasma space controllability. A processing system that uses this ion source will contribute to faster processing, highquality processing, and excellent-uniformity processing for ion beam etching, ion beam deposition, and ion beam sputter deposition. Many other applications are also expected. #

In order to break Moore's law by 3D integration, innovative solutions for inter-and intra-chip interconnections have to be developed. Inter-chip interconnection technologies using via-holes have been developed however their associated fabrication cost and yield are still unacceptable. To overcome these problems, wireless interconnects using capacitive coupling of small pads [1] or inductive coupling of on-chip spiral inductors [2] are proposed. With the former technique, since a pair of pads formed on different chips must couple with an insulation layer with the thickness of 1 to 2µm, the problems are not satisfactorily solved. The latter technique consumes large power of more than 10mW for a single interconnect. Therefore, expected requirements of over 1000 connections between chips cannot be realized in practice.Another bottleneck for 3D integration lies in the processing algorithm and architecture of conventional Neumann computers. Although living systems use a vast number of mutually connected neural cells that are sensitive to noise, these systems achieve highly sophisticated capabilities with sufficiently high reliability. To mimic biological systems, a processing architecture for aggregating information and making perspective judgment based on the advanced interconnection techniques is developed.From the view point of a complete system, global interconnects throughout whole chips and local parallel interconnects between adjacent chips are required. The former is used for system clocking over 10GHz as well as busses that enables synchronous processing and accessing to a G-byte database. The latter transfers 2D data such as image data, without the requirement of gathering and multiplexing.The proposed local wireless interconnection scheme (LWI) between chips utilizes the principle of magnetic coupling and resonance of on-chip spiral inductors. A circuit schematic and an inductor structure are shown in Fig. 14.4.1. TX consists of a switching MOST and a pulse shaper, and RX consists of an LC resonator, a detector, and a reconstruction FF. Current and voltage characteristics of the circuit are also shown in Fig. 14.4.1. To optimize transmission delay and power dissipation, the pulse width is set to the time when the inductor current (i L ) reaches its maximum value. FDTD analysis and circuit simulation show found that the inductor size (L ind ) should be larger than twice of the inductor distance (t chip ) to obtain a large enough coupling coefficient (k). These sizes are scalable under a constant current condition.The test chip is developed with a 0.25µm CMOS technology. Two chips are mounted on manipulators for measuring the transfer characteristics. Measured results are also shown in Fig. 14.4.1. A data rate of 800Mb/s is obtained at supply voltage of 2.5V and power consumption of 9mW. By circuit simulation using 0.18µm CMOS devices, 2Gb/s data rate are obtained with only 1mW power dissipation. The LWI can be applied to asynchronous interconnects corresponding to wires as well as synchronous systems using a ...

We present a new extended version of the R-matrix method for the calculation of continuum properties in which non-orthogonal orbitals are extensively used for describing both the target states and the R-matrix basis functions. In particular, a B-spline basis is used for the description of continuum states in the inner region and the target states may be obtained from independent calculations. This leads to a generalized eigenvalue problem but has the advantage of requiring much smaller bases for accurate representation of target wavefunctions and to achieve convergence in the close-coupling expansion. The present approach and its code are both applicable to a general atom and their efficiency for low-energy scattering processes is demonstrated by calculating the photoionization of Li. A detailed analysis of the resonance structure is given. Very good agreement with experimental data has been obtained, and considerable improvement in the description of resonances has been achieved in comparison with the standard R-matrix calculations.