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THIS PAPER will discuss a dynamic memory structure capable of constructing 1Mb VLSI 10 x lOmm memory chips in conventional photolithography, whose operational margin is within 2pm design. Figure 1 shows the structure of 2 bits of a one-transistor one-capacitor memory cell. The cell consists of a Quadruply Self Aligned (QSA) RIOSFET', a stacked high storage ~a p a c i t o r~'~ of tantalum oxide, a poly Si word line and an A1 bit line. aligned contact of QSA MOS' and high capacitance stacked capacitor structure, where F is the minimum feature size. This allows a relatively loose design rulc, thus avoiding short channel effect on subthreshold characteristics. 2 An ultimate cell area of 3F x 2F can be obtained by the selfShort channel effect and A1 alloy spike can he eliminated by the mutually self-aligned shallow and deep source and drain junctions of QSA MOSFET structure.by high dielectric constant of Ta2O5. Due to the small bit line capacitance Cg of the A1 bit line, a rcduced CB/C, ratio and hence large sensing signal can be obtained. The minimum N' area and large storage capacity-mean insensitivity to soft error is due to an 01 particle.

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