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In this paper, intermediate layer bonding technologies using SU-8 and BCB are successfully demonstrated. The bonding process, which consists of only several simple steps such as material deposition, exposure and development, as well as contact and bonding, can be carried out in a bonder at low temperature, e.g., somewhere between 120°C and 350°C. Benefits from this, integration of metal electrodes and wires between the bonding interfaces becomes possible. Moreover, since adhesive bonding does not necessitate extremely smooth contact surface, nor does it rely on the cleanliness of ambient environment, it is possible to carry out this process in a standard chemistry lab, and join different substrates without any pre-treatment. Initial inspection results showed that this method has a satisfactory yielding rate of more than 90%, and an acceptable bonding strength of above 2 MPa. The minimal thickness of the adhesive layer, which should retain the chips together after dicing, can be reduced to values between 6-10μm. For low-cost capacitive transducers, this is an attractive packaging technology. On the other hand, because SU-8 epoxy is an innovative building block for polymer devices, this method can also be used to construct complex micro systems.

The use of borosilicate glass for anodic wafer bonding to silicon is well established in industry. In this paper we present a matured approach, where a microstructured borosilicate glass thin-film instead of a bulk glass wafer is used as anodic bond layer. A glass layer with a thickness of 3-5 m is sufficient for a stable bond at very moderate bond parameters with bond voltages in the range of 30-60 V at standard bond temperatures of around 300°C and below. This enables the use of anodic bonding also for sensitive devices

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Microelectronic packaging continues the migration from wire bond to flip chip first level interconnect (FLI) to meet aggressive requirements for improved electrical performance, reduced size and weight. The interconnect pitch is being predicted by forecasts like ITRS to be reduced to 100 um and below for full array I/O layout. For wafer bumping, solder electroplating is commonly employed, especially for fine pitch applications. Wafer level chip scale packaging (WLCSP) typically utilizes solder sphere placement technology to manufacture the bumps. In WLCSP, pitch and solder ball size are usually much higher and the number of I/O much lower than for Flip Chip in Package (FCiP) applications. C4NP (Controlled Collapse Chip Connection New Process) has proven to be suitable for a broad range of solder bump pitches, encompassing FCiP to CSP bump dimensions. As the industry migrates to 300mm wafer processing and lead-free flip chip interconnect, C4NP is establishing itself as a viable solder bumping alternative. Due to its nature as a bump transfer technology, it is expected that the bumping yield will be very high, since filled molds can be inspected prior to solder transfer to the wafer. Yield is a major issue for the highest I/O applications like microprocessors. The under bump metallurgy (UBM) structure is a critical component of any solder interconnect system. The UBM typically provides three functions: adhesion to underlying dielectric and metal, barrier to protect the silicon circuitry, and a solder wettable surface