Articles you may be interested inLow-pressure inductively coupled plasma etching of benzocyclobutene with SF6/O2 plasma chemistry J. Vac. Sci. Technol. B 30, 06FF06 (2012); 10.1116/1.4758765Reduction of silicon recess caused by plasma oxidation during high-density plasma polysilicon gate etching Level set approach to simulation of feature profile evolution in a high-density plasma-etching system Profile evolution during polysilicon gate etching has been investigated with low-pressure high-density Cl 2 /HBr/O 2 plasma chemistries. Etching was performed in electron cyclotron resonance Cl 2 /HBr/O 2 plasmas as a function of HBr percentage in a Cl 2 /HBr mixture, using oxide-masked poly-Si gate structures. The linewidth was nominally 0.18 m, and the spacing between the two neighboring poly-Si lines was varied in the range ϳ0.2-10 m. In addition, the macroscopic open space of the oxide-masked sample was also varied over a wide range from Ϸ28% to Ϸ76%. As the HBr percentage in Cl 2 /HBr is increased from 0 to 100%, the linewidth shift ⌬L of poly-Si relative to the mask width ͑or the degree of sidewall tapering of poly-Si lines͒ first decreased linearly, passed through a minimum, and then increased considerably at above ϳ80%. In Cl 2 /O 2 plasmas without HBr addition, ⌬L was almost independent of the microscopic and macroscopic poly-Si open spaces although its value was relatively large; on the contrary, in HBr/O 2 plasmas, ⌬L increased with an increase of microscopic line spacing and/or the macroscopic open space of the sample. Comparisons of the etched profiles obtained in Cl 2 /HBr/O 2 plasmas with numerical profile simulations indicate that the strongly tapered sidewalls observed at high HBr percentages ͑տ80%͒ result from the simultaneous etch inhibitor deposition onto sidewalls during etching; moreover, such inhibitors are predicted to come from the plasma with a large sticking probability of ϳO(0.1). On the other hand, the relatively large ⌬L obtained in Cl 2 /O 2 plasmas is considered to be due to intrinsic sidewall tapering, rather than inhibitor deposition arriving from the plasma or redeposition of etch products desorbed from the surface in microstructures. Such intrinsic tapering is discussed in terms of the angular dependence of the Si etch yield.

Plasma–surface interactions occurring during overetch of polycrystalline silicon (poly-Si) gate etching with high-density HBr/O2 plasmas have been investigated by x-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM). The temporal variation of the gate oxide thickness measured by XPS indicates that both deposition of etch by-products SiBrxOy and oxidation of Si substrate underlying thin SiO2 occur during exposure to HBr/O2 plasmas. In particular, significant deposition of SiBrxOy, presumably coming from reactor walls, was observed at the beginning of the overetch step. Furthermore, TEM observations revealed that the profile evolution of oxide-masked poly-Si gates during overetch is limited by a sidewall deposition layer, which acts as an oxide mask for etching of poly-Si.

Plasma-surface interactions during etching of polysilicon gates in high-density HBr-based plasmas have been investigated by x-ray photoelectron spectroscopy and transmission electron microscopy. Significant deposition of etch by-products, SiBr x O y , presumably coming from reactor walls, was observed to occur on wafer surfaces at the beginning of the overetch in HBr/O 2 plasmas after the main etch of poly-Si. It was also found that this SiBr x O y deposition results in sidewall tapering of poly-Si gates because of the virtually increased mask width; moreover, the amount of SiBr x O y deposited and thus the etch anisotropy strongly depends on the concentration of O 2 in HBr/O 2 plasmas. On the basis of these observations, an approach to achieve nanometre-scale linewidth control during etching of poly-Si gates is discussed.

In this paper, we describe the effect of silicon substrate thickness on the characteristics of transmission lines fabricated using complementary metal-oxide-semiconductor (CMOS) technology. The S-parameters of the transmission lines on silicon-onmetal (SoM) and silicon-on-quartz (SoQ) are measured. The inductance of a microstrip line on SoM decreases as silicon substrate thickness is reduced, while that on SoQ is nearly constant for various substrate thicknesses. This fact is explained by the magnetic energy of the electromagnetic wave stored in the microstrip lines. Moreover, the loss of the microstrip line on SoM decreases as substrate thickness is reduced owing to a decrease in dielectric loss. In contrast, the characteristics of coplanar waveguides on both SoM and SoQ are constant for various substrate thicknesses.

We describe the effect of eddy currents flowing through a silicon substrate and a grounded metal plate on the characteristics of spiral inductors fabricated using complementary metal–oxide–semiconductor technology. The S-parameters of the spiral inductors on silicon-on-metal (SoM) and silicon-on-quartz (SoQ) are measured. The quality factor and inductance of the spiral inductor on SoM decrease as silicon substrate thickness decreases, because of an increase in the eddy current flowing through the metal plate. In the case of SoQ, the quality factor and inductance of the spiral inductor decrease as silicon substrate thickness decreases, because of a rapid increase in the eddy current flowing through the metal plate, if the distance between the inductor and the metal plate is shorter than the radius of the spiral inductor. Otherwise, the quality factor and inductance are almost constant for various substrate thicknesses, because of the small eddy current flowing through the metal plate.