One of the possible target applications of 3D-integration is the high performance computing (HPC). The improved performance of 3D-integrating can base on an Interposer with heterogeneous integration of special high performance fluidic cooling, individual power supply next to the microprocessor and a tailored packaging approach. This paper focuses on the reliability assessment of the interposer regarding the interaction of TSV, wiring and fluid channel integration based on current publications in correlation with the selected specifications for Interposer manufacturing. A further part is the correlation with initial results of stress simulation and measurements applied to the Interposer design specifications of cavities and interconnect features (used for sealing the cooling channels and as electrical interconnect). We give an overview of a new level of complexity of 3D integration and discuss certain failure mechanisms that can influence the performance of 3D integrated devices. We show that the prediction of failure locations becomes possible by the method of finite element modeling but with the necessity to obtain process specific material data as an input for the simulation. An overview shows the possibilites of residual stresses analyses on test vehicles by using special methods of Raman spectroscopy and fibDAC including interpretation challenges of gathered measurement data. Furthermore the application of a new method for fatigue testing is proposed and discussed

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With the anticipated slow-down of Moore's Law in the near future, three-dimensional (3D) packaging of microelectronic structures would enable to further increase the integration density required to meet the forecasted demands of future exa-scale computing, cloud computing, big data systems, cognitive computing, mobile communicatoin and other emerging technologies. Through-silicon vias (TSVs) are a pathway to provide electrical connections for signaling and power-delivery through 3D-stacked silicon (Si) microstructures. TSVs and related structures such as, e.g., interconnects and redistribution lines, however, induce stress in their proximity, namely upon electrochemical deposition and subsequent annealing, the latter due to the large mismatch in the coefficient of thermal expansion between Si and the TSV-filling materials used

Three-dimensional (3D) electronic systems enable higher integration densities compared to their 2D counterparts, a gain required to meet the demands of future exa-scale computing, cloud computing, big data systems, cognitive computing, mobile devices and other emerging technologies. Through-silicon vias (TSVs) open a pathway to integrate electrical connections for signaling and power delivery through the silicon (Si) carrier used in 3D-stacked microstructures. As a limitation, TSVs induce locally thermomechanical stress in the Si lattice due to a mismatch in the coefficients of thermal expansion between Si and the TSV-filling metals and therefore enforce temperature related expansion and shrinkage during the annealing cycle. This temperature-induced crowding and relaxation of the Si lattice in proximity of the TSV (called 'keep-out-zone' forbidden for active device positioning) can cause a variety of issues ranging from stress-induced device performance degradation, interfacial delamination or interconnect failures due to cracking of the bond or even of the entire Si microstructures at stress hotspots upon assembly or operation. Additionally also the interconnect structures induce stress that will overlap with the TSV induced stress