By introducing high-purity and low-temperature Ar annealing at 850 °C, atomically flat Si surfaces of silicon-on-insulator (SOI) and shallow-trench-isolation (STI)-patterned wafers were obtained. In the case of the STI-patterned wafer, this low-temperature annealing and subsequent radical oxidation to form a gate oxide film were introduced into the complementary metal oxide semiconductor (CMOS) process with 0.22 µm technology. As a result, a test array circuit for evaluating the electrical characteristics of a very large number (>260,000) of metal oxide semiconductor field effect transistors (MOSFETs) having an atomically flat gate insulator/Si interface was successfully fabricated on a 200-mm-diameter wafer. By evaluating 262,144 nMOSFETs, it was found that not only the gate oxide reliability was improved, but also the noise amplitude of the gate–source voltage related to the random telegraph noise (RTN) was reduced owing to the introduction of the atomically flat gate insulator/Si interface.

Atomically flattening technology was introduced to the widely used complementary metal oxide silicon process employing sallow trench isolation at the 0.22-μm technology node. Two methods were investigated. The first method is to apply the atomically flattening to the starting Si wafer, and the second method is to apply this just before forming the gate oxide. In both methods, atomically flat gate insulator/Si interface could be obtained, and the test array circuit for evaluating the electrical characteristics of many (>130,000) metal oxide semiconductor field effect transistors was successfully fabricated on an entire 200-mm-diameter wafer. By evaluating the test circuit, the noise amplitude of the gate–source voltage related to the random telegraph noise was reduced owing to introducing the atomically flat gate insulator/Si interface. The charge-to-breakdown of the gate oxide was also improved.

Low temperature (800 ºC - 900 ºC) Ar annealing for atomically flattening was applied to shallow trench isolation (STI)-patterned wafers where Si and SiO2 coexist on the wafer surface. During the Ar annealing, concentrations of H2O and O2 residual gases in the annealing ambience was maintained at low level less than 30 ppb. Such low temperature and clean Ar ambience can suppress oxidation and etching of Si surface as well as a decomposition of thick SiO2 film for device isolation. As a result, the atomically flat Si surface was obtained for the Si active pattern having STI edge by the Ar annealing at 800 ºC - 900 ºC. Owing to the introduction of the atomically flat Si/gate oxide interface, breakdown characteristic of the fabricated MOS capacitors was improved for the atomically flat devices.

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