We describe an RF MEMS contact switch technology that has been integrated above a 0.5um silicon RFCMOS-on-SOI process. This integration strategy combines a MEMS gold cantilever contact-switch with a custom silicon-on-insulator IC platform. This IC platform provides several power management functions critical for MEMS including high voltage generation, control and analog/digital/RF circuits... The technology also includes a waferlevel-package dielectric encapsulation process for the MEMS device which is hermetic and compatible with low cost packaging processes.

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Trends in wireless circuits toward more sophisticated digital signal processing increase demand for low-power low-supply highresolution analog-to-digital converters. This Σ∆ modulator converts the GSM IF spectrum using a low intermediate frequency (IF). The choice of the A/D resolution is crucial for accurate digital channel selectivity and at the same time to meet the requirements of the EDGE standard. The single-bit 2-2-cascaded modulator architecture is shown in Figure 3.2.1. Compared with highorder single-loop architectures, cascaded structures are more demanding in terms of component matching and amplifier gain. However, stability is ensured by cascading of low-order stages. The modulator uses a 13MHz clock to achieve an ultimate dynamic range of 84dB over 189kHz bandwidth (BW). Resonance is employed in the second stage to spread the zeros of the noise transfer function over the bandwidth and thus enhance noiseshaping efficiency. Although creating resonance requires a small capacitor, behavioral simulations show that the modulator SNR is not sensitive to the accuracy of the resonance path coefficient. The ideal modulator achieves 98dB peak SNR for a -1.3dB input and it remains >90dB for the worst-case of capacitor mismatch. The modulator SNR is ultimately limited by thermal noise. Power consumption is directly related to the total circuit capacitance. So accurate estimation of the thermal noise is essential to determine the value of the sampling and feedback capacitors in the first integrator [1]. Capacitors in the following stages are scaled down to minimize the power consumption.Coefficients maximizing the integrator output voltage swing are necessary for a low-power design [2]. However, high voltage swings require amplifiers capable of maintaining DC gain over the full output voltage swing. Behavioral simulations show that a minimum DC gain of 65dB in the three first OTAs is mandatory for the ideal SNR=98dB, while for the last stage a DC gain as low as 30dB is sufficient. Considering three main factors: gain, supply voltage and noise, a Miller-compensated amplifier is used in the three first stages (Figure 3.2.2-a) and a current-mirror amplifier is preferred for the last stage (Figure 3.2.2-b). The advantages of a Miller-amplifier are: high-gain, high-output swing and low input-referred noise. Joint system and circuitlevel design specifies the speed requirements of each OTA. The minimum unity-gain-bandwidth (UGBW) and slew-rate for the OTAs ensure the required settling accuracy. In two-stage amplifiers, in addition to the sensing common-mode (CM) feedback circuit, an extra CM-amplifier is needed [2]. Using a current-mirror with 20/3 ratio in the CM-amplifier allows high CM-UGBW and low bias current. However, care is taken to keep the associated extra pole as high as possible to preserve the CM-path phase margin. Regarding the stability and power considerations, the compensation capacitor of each Miller OTA is equal to the sampling capacitor of the next integrator. The compensation series resistors are nMO...

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