In this paper, a 32-bit RISC-V microcontroller in a 65-nm Silicon-On-Thin-BOX (SOTB) chip is presented. The system is developed based on the VexRiscv Central Processing Unit (CPU) with the Instruction Set Architecture (ISA) extensions of RV32IM. Besides the core processor, the System-on-Chip (SoC) contains 8KB of boot ROM, 64KB of on-chip memory, UART controller, SPI controller, timer, and GPIOs for LEDs and switches. The 8KB of boot ROM has 7KB of hard-code in combinational logics and 1KB of a stack in SRAM. The proposed SoC performs the Dhrystone and Coremark benchmarks with the results of 1.27 DMIPS/MHz and 2.4 Coremark/MHz, respectively. The layout occupies 1.32-mm 2 of die area, which equivalents to 349,061 of NAND2 gate-counts. The 65-nm SOTB process is chosen not only because of its low-power feature but also because of the back-gate biasing technique that allows us to control the microcontroller to favor the low-power or the high-performance operations. The measurement results show that the highest operating frequency of 156-MHz is achieved at 1.2-V supply voltage (V DD) with +1.6-V back-gate bias voltage (V BB). The best power density of 33.4-W/MHz is reached at 0.5-V V DD with +0.8-V V BB. The least current leakage of 3-nA is retrieved at 0.5-V V DD with −2.0-V V BB .

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In this paper, we discuss the characteristics of the InGaP/GaAs heterojunction phototransistors (HPTs) before and after the electrical stress at room temperature and assess the effectiveness of the emitter-ledge passivation. Although an electrical stress given to the phototransistors by keeping a collector current density of 37 A/cm2 for 1 hour at room temperature was too small to affect the room-temperature common-emitter current gain and photocurrent of both HPTs with and without the emitter-ledge passivation, they showed a significant decrease at 420 K due to the room-temperature electrical stress. Nevertheless, the room-temperature common-emitter current gain and photocurrent of the HPT with the emitter-ledge passivation were still higher than those of the HPT without the emitter-ledge passivation. The effectiveness of the emitter-ledge passivation against the electrical stress was more significant than that on the current gain in the dark. In addition to the electrical stress experiment, for a potential application of the InGaP/GaAs HPTs in space, we will irradiate the HPTs with 1-MeV electrons at the Japan Atomic Energy Agency. Both current gain and photocurrent decreased significantly after the electron irradiation. In contrast to the electrical stress, the damage due to the high-energy electron irradiation is a bulk-related phenomenon, and the emitter-ledge passivation does not seem to suppress the degradation.

Although the effects of electrical stress and temperature on the performance of the InGaP/GaAs heterojunction bipolar transistors (HBTs) have been widely studied and reported, little or none was reported for the InGaP/GaAs heterojunction phototransistors (HPTs) in the literature. In this paper, we discuss the temperature-dependent characteristic of InGaP/GaAs HPTs before and after electrical stress and assess the effectiveness of the emitter-ledge passivation, which was found to effectively keep the InGaP/GaAs HBTs from degrading at higher temperature or after an electrical stress. The emitter-ledge passivation is also effective keeping a higher optical gain even at higher temperature. An electrical stress was given to the HPTs by keeping the collector current at 60 mA for 15 min. Since the collector current density as an electrical stress is 24 A/cm2 and much smaller than the stress usually given to smaller HBTs for the stress test, the decreased optical gain was not observed when it was given at room temperature. However, when it was given at 420 K, significant decreases of the current gain and optical gain were observed at any temperature. Nevertheless, the emitter-ledge passivation was found effective in minimizing the decreases of the current gain and optical gain.