The effects of heavy-ion test conditions and beam energy on device response are investigated. These effects are illustrated with two types of test vehicles; SRAMs and power MOSFETs. In addition, GEANT4 simulations have also been performed to better understand the results

This paper describes application of the pulsed laser approach for identifying latch-up sensitive regions in CMOS circuitry. The utility of this approach for preliminary latchup screening of both COTS and spacequalified parts for applications in radiation environments is described. An application of hardening-by-design principles in which a space qualified CMOS product is modified, based on the pulsed laser results, to be latchup immune is presented in detail. The design modifications are described.

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The ESA SEU-Monitor, a DDR2 SDRAM and a power MOSFET have been irradiated at GSI with ions of energies from 80 to 1500 MeV/n. The results are compared to low energy (< 50 MeV/n) data

The main em phasis of this study is the investigation of the gate degradation or rupture, aiming to determine the nature of the so-called SEGR phenomena. This article presents experimental data showing heavy ions induced gate degradation in power MOSFETs. In the experiments, backside and front-side irradiations are performed. The heavy ions ranges are tuned in such way to control whether they hit the gate or not, during backside irradiation. Gate-to-source current Igss (4)) is measured versus Heavy Ions (H.I.) fluence 4>. Post-irradiation-Gate-StressTest (PGST) allows to measure breakdown voltage VBD(4)) as being decreasing with (H.I.) fluence. Based on these experimental results, an hypothesis of substrate-generated "hot carriers" impact overlap may explain gate degradation until SEGR triggering. This last hypothesis is supported by statistical approach model of heavy ions multiple impact.