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This paper describes a standardized high performance 640 by 512 readout integrated circuit [ROIC] for p-on-n detectors such as InSb, Heterojunction HgCdTe, QWIP, and InGaAs. The array is intended to support a wide range of systems through flexibility and advanced modes of operation. The 1SC9803 uses a flexible, programmable, multistage pipelined architecture to achieve a state-of-the-art ROIC suitable for applications ranging from hand-held infrared viewers to high-speed industrial imaging systems. A simplified default mode directly supports single output NTSC or PAL operation. Using the programmable mode, the 1SC9803 supports such advanced features as dynamic image transposition, dynamic windowing, multiple high-speed multiple output configurations, and signal 'skimming'. Both default and programmed modes support integrate-while-read and integrate-then-read snapshot operation, and variable gain. This array is part of the Indigo Systems family of standard ROICs that use a common architecture and electrical interface.

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This paper describes a high performance 320 by 256 readout integrated circuit (ROIC) designed for P-on-N short wave infrared (SWIR) detectors including InGaAs and HgCdTe, which also has the ability to operate at low input current levels with N-on-P detectors. The ROIC/FPA will support a wide range of system requirements from very low background applications (nightglow) to daytime high illumination conditions. To accommodate the wide scene dynamic range requirements, two selectable integration capacitors are used to control the input circuit transimpedance gain. A 1 OfF integration capacitor is used for low noise and low flux levels down to iO ft Lambert, corresponding to approximately 2x10'° phlcm2-sec for O.9m to 1.7tm spectral band using f/l.5 optics, assuming a 2856 Kelvin blackbody distribution. For higher flux levels, a O.2lpF integration capacitor can be selected, thus providing over a factor of 20 dynamic range. A capacitive feedback transimpedance amplifier (CTIA) provides a low noise detector interface circuit capable of operating at low input currents without frame-to-frame image lag. A sample and hold capacitor is also part of the input unit cell architecture, which allows the FPA to be operated in full frame snapshot mode and provides the maximum integration time available. The integration time is electronically controlled (gated) by an external clock pulse, and is adjustable from O.5.tsec to approximately the frame time of 33.3msec for 30Hz operation. This produces an additional factor of 66,000 to the total system dynamic range. The combination of integration time control and selectable integration capacitors accommodates over nine orders ofmagnitude in scene dynamic range.

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