Hermetic sealing is important regarding functionality and reliability for MEMS components. Typically this sealing is done at the wafer level using wafer bonding, which simultaneously also provides mechanical protective caps. An existing test structure for inner cavity pressure measurement, utilizing the pressure dependence of heat transfer in gasses, is used for detailed investigations of factors, which influence the inner cavity pressure in the wafer pre-processing and wafer bonding step itself. These investigations ultimately allowed optimized wafer processing, improved process control and reliability investigation.

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By using a trench isolated thick SOI process as base topology various optical and high voltage devices can be designed which are not or hardly possible in pnjunction isolated BCD processes. The trench isolation allows the construction of isolated photodiodes with excellent response even for red and infrared wavelengths. The thick SOI material enables the integration of vertical high voltage devices like NPN bipolar transistors. Together with a special collector design the buried layer and the sinker allow the integration of an IGBT device which is tune able between on-state and switching performance. Keywords-HV transistor, photo diode, Trench, thick SOI I.MOTIVATION A trench isolated thick Silicon-On-Insulator (SOI) technology [1] allows not only the easy high side and/or below ground operation of logic blocks and high voltage transistors, a further benefit is the possibility to integrate various optical and high voltage devices. Target of this work was to integrate new functionalities into the existing 650 V technology with a minimum of additional processing effort and a minimum of extra mask layers respectively. The dielectric isolation allows the integration of minority carrier injecting IGBT devices [2], [3], without any risk to inject carriers deeply into a common substrate. Also carriers generated by longer wavelengths in photodiodes deep in the silicon are confined and cross talk problems are reduced. Stacking of photodiodes is a further possibility that is made possible by the dielectric isolation. For integrated vertical devices the thick SOI layer allows breakdown voltages above 700 V. An example is a new vertical NPN transistor which was designed using existing design and process elements. II.STARTING POINT A trench isolated Bipolar-CMOS-DMOS (BCD) process on 55 µm SOI wafers containing 5, 7 and 20 V logic CMOS transistors, medium and high voltage n-channel DMOS and PMOS transistors as well as bipolar and other analogue devices like resistors and capacitors was the base for the development of new devices. Isolation, SOI thickness as well as doping concentrations are sufficient to achieve typical breakdown voltages above 700 V. Figure 1 schematically shows the dielectric isolation topology, consisting of the trench, the trench adjacent doping layer (sinker), the Buried OXide (BOX) and the highly doped buried layer above the BOX, together with the standard high voltage device, a 650 V n-channel quasi-vertical DMOS transistor. A pwell to n-device wafer (the upper wafer of the SOI wafer stack) junction diode in an isolated tub together with the sinker and buried layer dopings were used to build isolated photodiodes. A similar vertical construction as shown in Figure 1 was used to design a vertical NPN bipolar transistor. The pwell to n-device wafer junction allows blocking voltages above 700 V. To achieve such blocking voltages the drift region construction, slightly modified field plate structures and geometrical radii were reused in a slightly modified layout from the original high voltage DMOS.The high...

A fast identification method of membrane structure parameters is investigated for an early stage of the manufacturing process. The approach consists of performing optical measurement of the modal responses of the membrane structures. This information is used in an inverse identification algorithm based on a FE model.Device characteristics can be determined by measured modal frequencies which are fed into a model based on the FE simulations. The number of parameters to be identified is thereby generally limited only by the number of measurable modal frequencies. A quantitative evaluation of the identification results permits furthermore the detection of defects like cracks which cannot be classified within a FE model.The approach is validated by first measurements which have shown a good correlation between simulated and measured modal frequencies.

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