This study presents a new energy-efficient design for static random access memory (SRAM) using a low-power input data encoding and output data decoding stages. A data bit reordering algorithm is applied to the input data to increase the number of 0s that are going to be written into the SRAM array. Using SRAM cells which are more energy-efficient in writing a '0' than a '1' benefits from this, resulting in a reduction in the total power and energy consumptions of the whole memory. The input data encoding is performed using a simple circuit, which is built of multiplexers and inverters. After the read operation, data will be returned back to its initial form using a low-power data decoding circuit. Simulation results in an industrial and a predictive CMOS technology show that the proposed design for SRAM reduces the energy consumption of read and write operations considerably for some standard test images as input data to the memory. For instance, in writing pixels of Lenna test image into this SRAM and reading them back, 15 and 20% savings are observed for the energy consumption of write and read operations, respectively, compared with the normal write and read operations in standard SRAMs.

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A 0.16 m W, 2.3Volt multi-channel digitally controlled oscillaior (MICO) core is designed in a 0.6 micron CMOS process and its prototype design is mapped on an Altera FPGA that can be used for clock recovery applications. This architecture is suitable for digital wireless and cable hwnsceivers that use different bands for transmit and receive modes. As crysial-based-delay cells control its dominant propagation delay, we have obtained a reducedphase-noise in comparison to recently published analog-based DCOs.

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