This paper presents a new experimental setup (to our knowledge, the first ever) and results obtained with that setup from which we report extra combinational delays in an SRAM FPGA (Virtex-5) due to transient ionizing radiations. The results, obtained by proton irradiation at the TRIUMF laboratory, show that our setup can detect extra combinatorial delays as small as 40 ps, and that delays of more than 400 ps can affect the targeted FPGA. These results strongly suggest that delay faults can potentially be induced by transient ionizing radiations.

This paper aims at characterizing additional delays induced by ionizing radiation in Input/Output Blocks (IOBs) of Static Random-Access Memory Based Field Programmable Gate Arrays (SRAM-Based FPGAs), using measurement techniques based on ring oscillators (ROs). This characterization effort includes experiments performed with proton irradiation at TRIUMF on Xilinx devices (Virtex-5 and Artix-7). Results from these irradiation experiments show that RO period variations, up to 6.2 ns for Virtex-5 and 3.8 ns for Artix-7, could be induced. These results also reveal that the occurrence rate of events (namely delays and breaks) affecting ROs implemented in IOBs is approaching the rate observed when ROs are implemented in the FPGA core, even if the number of configuration bits dedicated to IOBs is significantly lower than for the FPGA core. These radiation test experiments are supported by emulation using similar RO-based measurement techniques and Xilinx SEU Controller as a fault injector. The fault injection experiments allow a better understanding of the behaviour of IOBs affected by additional delays due to configuration bit flips, which in many cases is similar to what can be observed with an incorrect parameter setting. Emulation experiments also reveal that many of the events modifying IOB behaviour are found to require multiple bit fault injection.

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This paper presents circuit level models that explain the extra combinational delays in a SRAM-based FPGA (Virtex-5) due to Single Event Upsets (SEUs). Several scenarios of extra combinational delays are simulated based on the circuit architecture of the FPGA core, namely Configurable Logic Blocks (CLBs) and routing. It is found that the main delay contribution originates from extra interconnection lines that are unintentionally connected to the main circuit path via pass transistors activated by SEUs. Moreover, longer delay faults observed on Input/Ouput Blocks (IOBs) due to SEU were investigated through simulations. In all cases, results are in close agreement with the ones obtained experimentally while exposing the FPGA to proton irradiation. Index Terms-Configurable logic element, extra combinational delays, IBIS model, Input/Ouput Blocks (IOBs), observed delay change (ODC), single event upset (SEU), SRAM-based FPGA.

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