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We fabricated field-emission vacuum microelectronic devices such as diode and triode devices, using high-resolution electron-beam lithography in combination with the reactive ion etching (RIE) technique. The turn-on voltage of the diode is 13 V, which is the lowest value reported for single-crystalline lateral silicon field-emission devices. An emission current of 1.4 µA was obtained at an anode bias of 40 V. Field emission was confirmed by the linearity of the Fowler-Nordheim plots. The anode current of the triode was effectively modulated as a function of gate voltage. The device stability results show that the proposed devices are stable and reproducible.

INTRODUCTIONIncessant efforts are being made for the shrinkage in metal-oxide-semiconductor (MOS) silicon devices. For dynamic random access memory (DRAM) technology, the reduction in capacitor cell size is crucial in device scaling. As DRAM cell size shrinks to giga bit scale, the capacitor height tends to increase even though a capacitor dielectric with high dielectric constant such as Ta 2 O 5 is adopted. Because the contact aspect ratio, defined as the contact height-towidth ratio, increases with capacitor height, the contact hole patterning becomes more difficult. The aspect ratio is expected to reach ϳ10 as the feature size shrinks to 0.15 m 1 In addition, poor metal film coverage may result upon deposition, which increases the contact resistance. One way of avoiding such a high aspect ratio contact process is to define contacts at the bitline level, prior to memory cell capacitor formation. The bitline acts as a data read and write path in the DRAM circuit. The tungsten/ titanium nitride/titanium (W/TiN/Ti) plug process has been widely used for pϩ and nϩ active contacts in DRAM. 2 Titanium reacts with silicon to form a low resistivity Ti-silicide phase, while the TiN barrier protects Ti against fluorine attack from WF 6 during CVD tungsten deposition.One of the major problems in this scheme has been the high-temperature post heat treatment, accompanied by the cell capacitor process. Employing Ta 2 O 5 as a capacitor dielectric typically requires post heat treatment to temperatures as high as 800°C in order to reduce the dielectric leakage current. The post heat treatment accompanies Ti-silicide film agglomeration and dopant loss at the silicide/silicon interface, which causes the contact property degradation. 2 In fact, the simulation shows that more than a 10% delay is expected in the circuit speed when the contact resistance increases by 300%.In this study, the apparent size-dependent increase in W/TiN/Ti to nϩ and to pϩ silicon contact resistance upon post heat treatment is examined. A finitedifference numerical scheme 3,4 is employed in order to analyze the effects of process parameters on the kinetics of Ti-silicide agglomeration, generally observed in transmission electron microscopy (TEM). This paper reports the anomalous scaling effect of tungsten/titanium nitride/titanium to (a) nϩ and (b) pϩ silicon electrical contact resistance in dynamic random access memory (DRAM) devices, upon post heat treatment following rapid thermal silicidation annealing. The electrical measurements on contacts of sizes ranging from 0.54 m to 0.18 m reveal that the increase in resistance becomes larger as the contact size decreases. Transmission electron microscopy (TEM) results show that the silicide film agglomeration proceeds more severely as the contact size decreases. To explain the size-dependent degradation of the contact resistance, numerical simulation of the shape evolution of the silicide film is performed. The results show that the poor film coverage, especially at the edge, accelerates the reduction rate in ...

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