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Through-silicon via (TSV) technology, an enabler for 3D ICs, has evolved, enabling thinner and shorter TSVs within substantially thinned wafers to achieve faster interconnects, large bandwidth density, and low power consumption. Yet, heat dissipation in 3D ICs becomes more and more challenging, especially in applications that require stacking of multiple processor and memory chips. Microfluidic cooling has been proposed as a solution to reject heat from 3D stacks that contain processor chips. However, current liquid cooling technology inevitably increases the wafer thickness, which is contrary to TSV technology trend. To date, little work has been done to optimize heat sink design to benefit TSV performance, and no attempt has been made to analyze the corresponding impact of a particular heat sink design on the performance of the electrical TSVs. A heat sink design without consideration of TSV performance can greatly diminish the advantages of 3D ICs. This paper presents a holistic cooling solution for 3D ICs, which not only meets thermal requirements, but also minimizes TSV parasitics that impact latency, bandwidth density, and power consumption. This paper will report: a) the design of a 3D-centric heat sink, b) the fabrication of the heat sink and associated high aspect ratio integrated TSVs, c) the thermal testing of the liquid-cooled heat sink and comparison to air-cooled heat sink, and d) the impact of the heat sink geometry on TSV capacitance.

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In this article we describe a novel cooling scheme utilizing a combination of fluidic (single-phase convection and phase change) and solid-state (superlattice cooler) techniques to simultaneously remove high background heat fluxes (,100 W/cm 2 ) over the entire chip and dissipate ultra high heat fluxes (,0.5-1 kW/cm 2 ) from multiple localized hot spots. This article focuses on the conceptual design to assess the feasibility of the proposed cooling scheme.

The reduction of interfacial resistance continues to be a significant challenge in thermal management of semiconductor and other microscale devices. Current state-of-the-art thermal interface materials (TIMs) have resistances in the range of 5–10 mm2·K/W. At these values, particularly for the emerging highly nonhomogeneous materials, standard measurement techniques often fail to provide accurate results. This paper describes the use of infrared microscopy for measuring the total thermal resistance across multiple interfaces. The method is capable of measuring samples of wide ranging resistances with thicknesses ranging from 50–250 μm. This steady-state technique has several advantages over other methods, including the elimination of the need for intrusive temperature monitoring devices like thermocouples at the area of interest and the need for a priori knowledge of the specific heat and density of the materials of interest, as in the transient techniques for determining thermal resistances. Results for three different commercially available TIM and uncertainty analysis are presented.