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The piezoelectronic transduction switch is a novel device with high potential as a post-CMOS transistor due to its predicted multi-GHz, low voltage performance on the VLSI-scale. However, the operating principle of the switch has much wider applicability. We use theory and simulation to optimize the device across a wide range of length scales and application spaces and to understand the physics underlying its behavior. We show that the four-terminal VLSI-scale switch can operate at a line voltage of 115 mV while as a low voltage-large area device, ≈200 mV operation at clocks speeds of ≈2 GHz can be achieved with a desirable 10 4 On/Off ratio-ideal for on-board computing in sensors. At yet larger scales, the device is predicted to operate as a fast (≈250 ps) RF switch exhibiting high cyclability, low On resistance and low Off capacitance, resulting in a robust switch with a RF figure of merit of ≈4 fs. These performance benchmarks cannot be approached with CMOS which has reached fundamental limits. A combination of finite element modeling and ab initio calculations enables prediction of switching voltages for a given design. A multivariate search method then establishes a set of physics-based design rules, discovering the key factors for each application. The results demonstrate that the piezoelectronic transduction switch can offer fast, low power applications spanning several domains of the information technology infrastructure.

ABSTllACTWe report a comprebensive characterization of a 90 nm CMOS technology with CdSiCOH low-k interconnect BEOL. Signifcant material and integration engineering have led to the highest reliability, without degrading the performance expected from low-k. Results are presented on every aspect of BEOL and chippackage reliability, yields, low-k f i l m parameters, BEOL capacitances and circuit delays on functional chips. All results meet or exceed OUT concurrent 90 nm Cu/FTEOS technology, and support extendibility to 65 nm.