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Lead titanate (PT) sols were prepared using propanediol, butanediol, or pentanediol solutions of lead acetate trihydrate and titanium diisopropoxide bis(acetylacetonate). Precursor sols for PbZr0.53Ti0.47O3 (PZT) films were prepared from propanediol solutions, with zirconium tetrapropoxide being used as the zirconium source. Films were formed by spin‐coating the sols onto silicon and platinized silicon substrates; the resulting gel layers were converted to ceramic films by adopting a two‐stage heating schedule with final firing temperatures of 600–700°C. Information on film crystallization, microstructure development, and electrical properties is presented for both compositions. The limiting thickness of surface‐smooth crack‐free single‐layer films was ∼1 μm. The PT films exhibited a “linear” polarization‐electric field (P‐E) response, while the PZT films gave rise to characteristic ferroelectric P‐E hysteresis loops. A 0.5 μm thick single‐layer PZT film exhibited remanent polarization (Pr) values of ∼34 μC·Cm−2, with a coercive field (Ec) of ∼45 kV·Cm−2; the relative permittivity (ɛr) and the dissipation factor (D) were ∼1250 and 0.07. For a 1 μm single‐layer PZT film, the respective values were Pr∼19 μC∼Cm−2, Ec∼40 kV∼Cm−2, ɛr∼750, and D= 0.03.

Single layer Pb(Zr0.53Ti0.47)O3 films up to 0.7 μm thick have been prepared from air-stable titanium and zirconium precursors using a diol-based sol-gel route. Information on film crystallization, surface microstructure, and electrical properties under different firing temperatures and three different heating rates including rapid thermal annealing are presented. Films exhibited (111) preferred orientation, the extent of which reduced with increasing firing temperature or heating rate. It is possible that a PbPtx interfacial reaction product was formed during the prefiring step at 350 °C and this, together with the influence of the 111 bottom platinum electrode, contributed to (111) orientation in the PZT films. Surface microstructure was also influenced by firing temperature and heating rate as well as by film thickness. The 0.4 μm thick films used for electrical measurement had a grain size of ⋚0.1 μm, whereas 0.7 μm thick films made from concentrated sols exhibited “rosette” microstructures with grain sizes up to 0.5 μm. Among the three firing schedules studied, directly inserting the gel coatings in a furnace preset at 700 °C produced films with the most favorable electrical properties. A 0.4 μm thick film gave rise to a remanent polarization, Pr, of 33 μC cm−2 coercive field, Ec, of 46 kV cm−1; relative permittivity, ∊r, of 1100; and dissipation factor, D, of 0.05. For a 0.7 μm single layer film, the respective values were 21 μC cm−2, 36 kV cm−1, 1300, and 0.05.

A recently developed diol sol-gel route has been modified in order to produce multilayer PbZr 0.53 Ti 0.47 O 3 films on platinized sapphire substrates. Up to 20 depositions of a 1.1 M sol were carried out leading to a final film thickness of 10 mm. A similar thickness could be achieved from 12 coatings of a more concentrated 1.6 M sol. Decomposition and crystallization of the multilayer coatings were performed using a two-stage prefiring sequence, at 350 ± C and 600 ± C, followed by a final firing step at 700 ± C. Ferroelectric remanant polarization increased with increasing film thickness to a value of 40 mC cm 22 for a 10 mm film, with a corresponding coercive field of 30 kV cm 21 ; the relative permittivity of this film was ϳ1000 and the dissipation factor 0.04. The thickness dependence of relative permittivity could be modeled on a simple series capacitor circuit representing the ferroelectric Pb(Zr, Ti)O 3 (PZT) film and low-permittivity interface layers; but other possible contributory factors are also discussed.

IntroductionPixel scaling trend on CMOS image sensor (CIS) calls for a novel technology to improve sensor's optical response being blocked or interfered by metal layers in traditional front-side illumination (FSI) sensor structure. Recently, backside illumination (BSI) sensor technology gradually becomes the main-stream CIS process to achieve virtually 100% fill-factor to boost the optical response and enhance optical angular response due to a shorter optical path. In this paper, a leading-edge N65 0.9μm pixel BSI technology using 300mm bulk silicon wafer is reported with process breakthroughs. Challenges for pixel-size scaling beyond 0.9μm are discussed. Technology OverviewBuilding image sensors with a BSI technology is an effective approach to maintain pixel size scaling trend without sacrificing sensor performance [1][2][3][4]. For pixel sizes less than ~1.75μm, BSI sensor's optical parameters, such as sensitivity, quantum efficiency (QE), optical cross-talk, angular response etc., can be significantly improved over FSI's due to no optical diffraction or blocking effect by routing metal layers along the optical path. Despite of the simple concept to flip the physical sensor with metal structure upside-down, developing the BSI manufacturing process is not a trivial task. Several key process modules that did not exist in traditional IC processes were created and carefully controlled to achieve mass-production capability. The following are the descriptions of the BSI processing and the related module performance.A schematic of BSI process flow is shown in Fig.1. P/P+ epi wafers provide a cost-effective solution compared with SOI wafers. After Back-End-of-Line (BEOL) process is completed, a device wafer runs through a planarization process and is bonded with a carrier wafer. The bonded wafer is then mechanically and chemically thinned down from the bottom side of the device wafer to the target thickness. The new backside Si surface is implanted with a shallow P+ layer followed by laser anneal for dopant activation. Backside antireflection (BARC) layers are coated to further enhance optical sensitivity. Pad opening, color filter array, and packaging process are performed to complete the BSI sensor manufacturing.The aforementioned process utilizes several new tools uncommon to traditional CMOS technology and that poses certain challenges in the process development. The major steps are wafer bonding, thin-down process, and laser anneal. Wafer bonding mainly determines the maximum mechanical stress the BSI wafers can tolerate in following processes including thermal treatment and packaging. It also imposes a certain stress to the bonded device and carrier wafers. Bond voids at the bonding interface and wafer distortion are key parameters of the bonding process. Fig. 2 shows a bonding process window obtained to achieve voidfree and good distortion. Optimized with a bond anneal process, 300mm wafers have been proven to withstand complete BSI process, color filter array (CFA), and packaging.For wafer thin-down process, f...