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Device charging in the ion implantation is evaluated by using two different types of electrically erasable-programmable read-only memory (EEPROM) devices and two different types of metal-oxide-semiconductor (MOS) capacitors. The averaged charging voltage is measured by the turn-on voltage shift (ΔV T) of a grounded source EEPROM, while the transient charging effect is detected by a floating source EEPROM. The yield of the MOS capacitor reaches its maximum when the grounded source EEPROM shows the minimum ΔV T. The effects of the charge-collecting electrode area and substrate type of the MOS capacitor are also examined.

This report describes improvements in the trench DRAM technology for 0.15 pm groundrule and beyond. The optimum cell layout is 8F2 with a cell area of only 0.18 pm' for a 0.15 pm groundrule. High node capacitance and low node contact resistance are demonstrated for these small groundrules. By using a dual gate oxide and self-aligned support junctions, the different performance requirements of array and support devices can be met. These technology features and their extendibility are evaluated on a 256Mb DRAM design.Introduction The self-aligned buried strap (BEST) trench DRAM cell [1][2] can be scaled for future DRAM generations. Trench capacitors provide a more planar surface than stacked capacitors [2], resulting in a larger process window for lithography and etch.