The noise performance of CMOS image sensors has improved significantly. The most popular way to reduce readout circuit noise is amplifying pixel output using a preamplifier at the foremost stage of readout chain to suppress the noise of following readout chains in high analog gain [1][2][3]. Another approach is multiple sampling which can reduce temporal noise of pixel and readout circuit by sampling the same pixel repeatedly and processing (generally averaging) the sampled data [4,5]. However, both approaches require additional circuitry in the column readout chain which requires extra silicon area and power consumption. Furthermore, it is hard to implement a decent per-column amplifier in a small pixel pitch sensor, such as 1.4µm pixel, because of narrow layout space. In addition, the second approach requires longer readout time proportional to the number of samples. This paper presents a cost-effective low noise CMOS image sensor readout chain using pseudo-multiple sampling technique.The proposed pseudo-multiple sampling technique is described in Fig. 22.2.1. The basic concept of pseudo-multiple sampling is dividing an A/D conversion into several lower resolution A/D conversions. The quantization step of each lower resolution A/D conversion is M times larger than that of normal A/D conversion where M is the number of pseudo-multiple sampling. Each quantization level of lower resolution A/D conversion has 1 LSB offset of normal A/D conversion to ensure the final result has the same resolution of normal A/D conversion. The final result can be calculated by adding all lower resolution A/D conversion results.The output noise of each lower resolution A/D conversion is approximately 1/M times lower than that of normal A/D conversion, when the input noise standard deviation is higher than the quantization step of lower resolution A/D conversion. Therefore, the output noise of the pseudo-multiple sampling A/D conversion is 1/√M times lower than that of normal A/D conversion, if the noise is completely uncorrelated. It is same as the conventional multiple sampling. However, the noise reduction effect of the pseudo-multiple sampling is limited, although the number of sampling is increased. It is because if the quantization step of lower resolution A/D conversion is higher than the input noise standard deviation, some of lower resolution A/D conversion cannot express the input noise properly. Figure 22.2.2 is the noise reduction simulation result of the conventional multiple sampling and the pseudo-multiple sampling using an ideal A/D converter with input noise applied. The noise is assumed white Gaussian having standard deviation of σ in in normal A/D conversion LSB unit. The simulation result shows the noise reduction performance of the pseudo-multiple sampling is almost same as that of the conventional multiple sampling up to M=σ in , and the output noise is saturated to 0.75×√σ in when M is higher than 4σ in .The pseudo-multiple sampling can be implemented using a conventional single slope ADC structure by altering o...

We propose a dual-channel interface architecture that allocates high and low transition-density bit streams to two separate channels. The transmitter utilizes the stacked drivers with charge-recycling to reduce the power consumption. The direct current (DC)-coupled receiver front-end circuits manage the common-mode level variations and compensate for the channel loss. The tracked oversampling clock and data recovery (CDR), which realizes fast lock acquisition below 1 baud period and low logic latency, is shared by the two channels. Fabricated in a 65-nm low-power complementary metal-oxide semiconductor (CMOS) technology, the dual-channel transceiver achieves 12-Gb/s data rate while the transmitter consumes 20.43 mW from a 1.2-V power supply.

This paper presents a chip-level integration of radio-frequency (RF) microelectromechanical systems (MEMS) air-suspended circular spiral on-chip inductors onto MOSIS RF circuit chips of LNA and VCO using a multi-layer UV-LIGA technique including SU-8 UV lithography and copper electroplating. A high frequency simulation package, HFSS, was used to determine the layout of MEMS on-chip inductors with inductance values close to the target inductance values required for the RF circuit chips within the range of 10%. All MEMS on-chip inductors were successfully fabricated using a contrast enhancement method for 50 lm air suspension without any physical deformations. High frequency measurement and modeling of the integrated inductors revealed relatively high quality factors over 10 and self-resonant frequencies more than 15 GHz for a 1.44 nH source inductor and a 3.14 nH drain inductor on low resistivity silicon substrates (0.014 X cm). The post-IC integration of RF MEMS onchip inductors onto RF circuit chips at a chip scale using a multi-layer UV-LIGA technique along with high frequency measurement and modeling demonstrated in this work will open up new avenues with the wider integration feasibility of MEMS on-chip inductors in RF applications for costeffective prototype applications in small laboratories and businesses.

No abstract

No abstract