13.1 A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology

Park, Jong‐Seok; Subramanian, S.; Lampert, Lester; Mladenov, Todor; Klotchkov, Ilya; Kurian, Dileep; Juarez-Hernandez, Esdras; Perez-Esparza, Brando; Kale, Sirisha; Beevi, K T Asma; Premaratne, Shavindra; Watson, Thomas; Suzuki, Satoshi; Rahman, Md. Shafiqur; Timbadiya, Jaykant; Soni, Saksham; Pellerano, Stefano

doi:10.1109/isscc42613.2021.9365762

“…This variability is clearly observed in recent cryo-CMOS integrated circuits for qubit interfacing, as SH ranged from 1 to 3 K in a 40-nm bulk-CMOS high-speed ADC with low power density [26] to more than 10 K in a 22-nm FinFET microwave driver [12]. As device geometry and power density differ considerably between advanced bulk CMOS nodes and the previously studied mature technologies, it is necessary from a modeling perspective to characterize SH on devices better resembling those employed in practical cryo-CMOS designs [26]- [29], both in geometry and power density. Understanding the impact of SH is especially crucial for the cryo-CMOS low-noise amplifiers (LNA) necessary for the detection of the weak signals from quantum processors, as an increase of the device temperature of only a few Kelvin can strongly affect the noise performance, e.g., in a thermal-noiselimited amplifier in which the noise is directly proportional to the device temperature.…”

Section: Imentioning

confidence: 99%

Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures

Hart

¹

,

Babaie

²

,

Vladimirescu

³

et al. 2021

IEEE J. Electron Devices Soc.

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This work presents a self-heating study of a 40nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel and in the surrounding silicon substrate, using the gate resistance and silicon diodes as sensors, respectively. Since self-heating depends on factors such as device geometry and power density, the test structure characterized in this work was specifically designed to resemble actual devices used in cryogenic qubit control ICs. Severe self-heating was observed at deep-cryogenic ambient temperatures, resulting in a channel temperature rise exceeding 50 K and having an impact detectable at a distance of up to 30 µm from the device. By extracting the thermal resistance from measured data at different temperatures, it was shown that a simple model is able to accurately predict channel temperatures over the full ambient temperature range from deep-cryogenic to room temperature. The results and modeling presented in this work contribute towards the full selfheating-aware IC design-flow required for the reliable design and operation of cryo-CMOS circuits.

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“…The junction geometry opens space between modules to route the gate lines and/or to place cryogenic classical electronics in the quantum processor plane [10,34]. Fabricating the qubits and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds in error-correction protocols, and offer potential solutions to wiring and layout challenges [7,[77][78][79][80][81]. Integrating classical and quantum devices monolithically, using CMOS processes, enables the quantum processor to profit from the most mature industrial technology for the fabrication of large-scale circuits [35].…”

Section: Discussionmentioning

confidence: 99%

Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity

Crawford¹,

Cruise²,

Mertig³

et al. 2022

Preprint

0

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Inspired by the challenge of scaling up existing silicon quantum hardware, we investigate compilation strategies for sparsely-connected 2d qubit arrangements and propose a spin-qubit architecture with minimal compilation overhead. Our architecture is based on silicon nanowire split-gate transistors which can form finite 1d chains of spin-qubits and allow the execution of two-qubit operations such as Swap gates among neighbors. Adding to this, we describe a novel silicon junction which can couple up to four nanowires into 2d arrangements via spin shuttling and Swap operations. Given these hardware elements, we propose a modular sparse 2d spin-qubit architecture with unit cells consisting of diagonally-oriented squares with nanowires along the edges and junctions on the corners. We show that this architecture allows for compilation strategies which outperform the bestin-class compilation strategy for 1d chains, not only asymptotically, but also down to the minimal structure of a single square. The proposed architecture exhibits favorable scaling properties which allow for balancing the trade-off between compilation overhead and colocation of classical control electronics within each square by adjusting the length of the nanowires. An appealing feature of the proposed architecture is its manufacturability using complementary-metal-oxide-semiconductor (CMOS) fabrication processes. Finally, we note that our compilation strategies, while being inspired by spin-qubits, are equally valid for any other quantum processor with sparse 2d connectivity.

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“…This variability is clearly observed in recent cryo-CMOS integrated circuits for qubit interfacing, as SH ranged from 1 to 3 K in a 40-nm bulk-CMOS high-speed ADC [26] to more than 10 K in a 22-nm FinFET microwave driver [12]. As device geometry and power density differ considerably between advanced bulk CMOS nodes and the previously studied mature technologies, it is necessary from a modeling perspective to characterize SH on devices better resembling those employed in practical cryo-CMOS designs [26]- [29], both in geometry and power density. Understanding the impact of SH is especially crucial for the cryo-CMOS low-noise amplifiers (LNA) necessary for the detection of the weak signals from quantum processors, as an increase of the device temperature of only a few Kelvin can strongly affect the noise performance, e.g., in a thermal-noiselimited amplifier in which the noise is directly proportional to the device temperature.…”

Section: Imentioning

confidence: 99%

Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures

Hart¹,

Babaie²,

Vladimirescu³

et al. 2021

Preprint

View full text Add to dashboard Cite

This work presents a self-heating study of a 40nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel and in the surrounding silicon substrate, using the gate resistance and silicon diodes as sensors, respectively. Since self-heating depends on factors such as device geometry and power density, the test structure characterized in this work was specifically designed to resemble actual devices used in cryogenic qubit control ICs. Severe self-heating was observed at deep-cryogenic ambient temperatures, resulting in a channel temperature rise exceeding 50 K and having an impact detectable at a distance of up to 30 µm from the device. By extracting the thermal resistance from measured data at different temperatures, it was shown that a simple model is able to accurately predict channel temperatures over the full ambient temperature range from deep-cryogenic to room temperature. The results and modeling presented in this work contribute towards the full selfheating-aware IC design-flow required for the reliable design and operation of cryo-CMOS circuits.

show abstract

13.1 A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology

Cited by 63 publications

References 6 publications

Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures

Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures

Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity

Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures

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