A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS

Digital-to-Frequency Converters With a DTC: Theoretical Analysis of the Output SFDR

“…The DTC also introduces random jitter, but this is less of a concern, since the DTC acts on the edges of a divided signal (the pulse-output DFC can be seen as a frequency divider). The random jitter produced in recent DTC implementations is in the order of ∼ 100 fs [25], [41], [54], so that the DTC contribution to the output random jitter for an output frequency of 1 GHz would be only 0.01%. Therefore, in this work we will focus only on deterministic jitter, which is manifested in the form of spurs.…”

“…Where N DTC − 2 is the number of bits of each fine DTC. The INL is a function ofDW , so its expected value E {|INL (DW )|} should be calculated using (54). To simplify calculations, for high enough N DTC ,DW can be approximated as a continuous-type random variable, with uniform probability density function (p.d.f.…”

A 31-$\mu$ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS

“…The literature also reports a DTC used to dither the reference clock over an ADPLL to suppress its spurs at near integer-N channels [17], as well as ADPLLs achieving fractional-N operation based on a conventional integer-N PLL architecture [7], [10]. The dynamic range of the DTC can be relaxed by using multi-phase outputs from a DCO divider or a coarse-fine DTC architecture [6], [12]. It can further be reduced with an assistance of a phase interpolator (PI) in the feedback path [7].…”

Digital-to-Time Converters for spur correction in Digital Frequency Synthesis

“…The work [61] proposes a 100 MHz 10−bit DTC, based on digitally controlled delay lines (Fig. 2.11), made out of CMOS inverters loaded by a capacitor array.…”

“…A similar DTC in [61] has been used in the Direct Digital Synthesizer (DDS) in [28], based on ∆Σ fractional dividers (Fig. 2.12).…”