A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS

Lee, Changhyeon; Kabalican, Lindel; Ge, Yan; Kwantono, Hendra; Unruh, Greg; Chambers, Mark; Fujimori, Ichiro

doi:10.1109/jssc.2014.2371136

Cited by 14 publications

(6 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Table II shows the performance comparison between stateof-the-art LC-based frequency synthesizers. Our proposed solution is the smallest, except for [41] which occupies almost the same area. Our solution has moderate jitter performance (in general 10 dB worse than high-end solutions), since it was compromised while trading for the area.…”

Section: Resultsmentioning

confidence: 93%

“…A comparison of the FoM jitter shows that our RO-based ADPLL is the best in its class and our transformer-based ADPLL provides an additional 11-dB improvement, being comparable in performance to similar-area LC PLLs [13], [41] and only 8-10 dB worse FoM jitter than the best-in-class, but of large-area, wireless (narrow-band) LC PLLs [38], [39]. Moreover, important parameters, such as frequency pushing (not universally reported), which can be translated as frequency sensitivity to its supply, is intrinsically superior in LC tank DCOs (and also in our case) than in any RO-based.…”

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

An Ultracompact 9.4–14.8-GHz Transformer-Based Fractional-N All-Digital PLL in 40-nm CMOS

Ximenes

Vlachogiannakis

Staszewski

2017

IEEE Trans. Microwave Theory Techn.

View full text Add to dashboard Cite

In this paper, we apply various area reduction techniques on an inductor-capacitor (LC)-tank oscillator in order to make its size comparable to that of ring oscillators (ROs), while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The resulting oscillator employs a proposed ultracompact split transformer topology that provides a 1:2 passive voltage gain and is less susceptible to common-mode electromagnetic interference than are regular high-quality-factor LC tanks, thus making it desirable in systemon-a-chip environments. The oscillator, together with a proposed dc-coupled buffer, is incorporated within an all-digital phaselocked loop (ADPLL) intended for wireline, digital clocking, and less stringent wireless systems. The ADPLL architecture introduces a look-ahead time-to-digital converter that exploits a deterministic phase prediction to reduce power consumption and phase detection complexity. The ADPLL is realized in 40-nm CMOS and has the smallest reported area of 0.0625 mm 2 among LC-tank oscillators while providing fractional-N operation, wide tuning range of 45% (from 9.4 to 14.8 GHz), very low voltage supply sensitivity of 80 MHz/V, and integrated figure-of-merit jitter (FoM jitter) better than −230 dB. A separate identical ADPLL was implemented using an RO instead, for completeness and systematic comparisons. Index Terms-All-digital phase-locked loop (ADPLL), digitally controlled oscillator (DCO), inductor-capacitor (LC)-tank oscillator, ring oscillator (RO), time-to-digital converter (TDC), transformer. I. INTRODUCTION M ONOLITHIC frequency synthesizers have been used as key building blocks in a wide range of applications. In digital data communications, they are responsible for generating GHz-level frequency carriers either through an inductor-capacitor (LC)-tank oscillator or a ring oscillator (RO), depending on the application's set of requirements and IC implementation tradeoffs. Due to their small silicon area, wide tuning range and performance improvements with scaling, ROs are widely adopted in wireline systems. However, their intrinsically poor phase Manuscript

show abstract

Section: Resultsmentioning

confidence: 93%

Section: Resultsmentioning

confidence: 99%

An Ultracompact 9.4–14.8-GHz Transformer-Based Fractional-N All-Digital PLL in 40-nm CMOS

Ximenes

Vlachogiannakis

Staszewski

2017

IEEE Trans. Microwave Theory Techn.

View full text Add to dashboard Cite

show abstract

“…To further evaluate the effect of the substrate resistance on the Q-factor of the transformer, a simplified equivalent circuit model shown in Fig. 7(c) [32] is used. 3 The substrate resistance 2R sub pertains to the area underneath the coils.…”

Section: B Special Arrangement Of Native Layer and Its Em Analysismentioning

confidence: 99%

A Compact 0.2–0.3-V Inverse-Class-F₂₃ Oscillator for Low 1/f ³ Noise Over Wide Tuning Range

Siriburanon

et al. 2022

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

We introduce a new mode of oscillation in an LCtank: an inverse class-F 23 . In contrast to the conventional class-F oscillators, in which a high value of the real impedance (i.e., resistance) is presented to the third (in class-F 3 ) or/and to the second (in class-F 2 /class-F 23 ) oscillator harmonics via an auxiliary resonance, here low resistive impedances (resembling a non-ideal short) are presented at both the second and third harmonics. This is made possible by tight magnetic coupling in the differential and common modes, respectively, afforded by a new compact 2:3 transformer. Being largely free from the harmonics in the voltage waveform and their possible deleterious phase shift effects on the flicker noise up-conversion, the phase noise performance in the flicker and thermal regions is further improved by narrowing the conduction angle. The 2:3 step-up transformer also provides a high passive gain to help with the startup in face of low supply. The switched-capacitor banks and cross-coupled transistor pair are carefully integrated under the transformer with a special arrangement of native (high-resistivity) substrate layer to mitigate their effect on the oscillation while reducing the area by 30%. The proposed digitally controlled oscillator (DCO) is implemented in 28-nm CMOS and achieves −95 dBc/Hz and −118 dBc/Hz at 100 kHz and 1 MHz offsets, respectively, while operating at a 0.3 V supply. The measured 1/ f 3 corner stays within 60 to 100 kHz over the 35% tuning range (TR) (from 2.02 to 2.87 GHz). This results in a figure-of-merit (FoM) with normalized TR (FoM T ) of −196 and −199 dB at 100 kHz and 1 MHz offsets, respectively, is a record in the space of ≤0.5 V and ≤1 mW.

show abstract

“…We surmise that observation would extrapolate to transformers. This reasoning concludes that further area reduction in the transformer-/inductor-dominated TX would only be possible by making the active devices (i.e., the remainder of the constituting components) somehow "disappear" beneath these passives [27]. Naturally, this needs to be done without degrading the precious Q-factor and other performance parameters.…”

Section: A Vertical Layout Integrationmentioning

confidence: 99%

“…To gain deeper understanding, Fig. 5(a) illustrates the simplified equivalent circuit of the transformer model without the PGS and is compared with that of the transformer model in The overall Q-factor calculation of the transformer's primary winding is given by (2), based on a method in [27]. The secondary winding inductance L s can be analyzed similarly as…”

Section: A Vertical Layout Integrationmentioning

confidence: 99%

A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network

Kuo

Ferreira

Chen

et al. 2017

IEEE J. Solid-State Circuits

105

View full text Add to dashboard Cite

We present an ultra-low-power Bluetooth lowenergy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F 2 digital power amplifier (PA), featuring high efficiency. Low 1/ f DCO noise allows the ADPLL to shut down after acquiring lock. The receiver operates in discrete time at high sampling rate (∼10 Gsamples/s) with intermediate frequency placed beyond 1/ f noise corner of MOS devices. New multistage multirate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise, and low power consumption. An integrated on-chip matching network serves to both PA and low-noise transconductance amplifier, thus allowing a 1-pin direct antenna connection with no external band-selection filters. The TRX consumes 2.75 mW on the RX side and 3.7 mW on the TX side when delivering 0 dBm in BLE. Index Terms-All-digital PLL (ADPLL), Bluetooth low energy (BLE), digitally controlled oscillator (DCO), discrete-time (DT) receiver (RX), Gaussian frequency shift keying (GFSK), intermediate frequency (IF), Internet of Things (IoT), low-power (LP) transceiver (TRX), matching network, transmit/receive (T/R) switch, transmitter (TX).

show abstract

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS

Cited by 14 publications

References 25 publications

An Ultracompact 9.4–14.8-GHz Transformer-Based Fractional-N All-Digital PLL in 40-nm CMOS

An Ultracompact 9.4–14.8-GHz Transformer-Based Fractional-N All-Digital PLL in 40-nm CMOS

A Compact 0.2–0.3-V Inverse-Class-F₂₃ Oscillator for Low 1/f ³ Noise Over Wide Tuning Range

A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network

Contact Info

Product

Resources

About

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS

Cited by 14 publications

References 25 publications

An Ultracompact 9.4–14.8-GHz Transformer-Based Fractional-N All-Digital PLL in 40-nm CMOS

An Ultracompact 9.4–14.8-GHz Transformer-Based Fractional-N All-Digital PLL in 40-nm CMOS

A Compact 0.2–0.3-V Inverse-Class-F23 Oscillator for Low 1/f 3 Noise Over Wide Tuning Range

A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network

Contact Info

Product

Resources

About

A Compact 0.2–0.3-V Inverse-Class-F₂₃ Oscillator for Low 1/f ³ Noise Over Wide Tuning Range