We present an ultra-low-power Bluetooth lowenergy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F 2 digital power amplifier (PA), featuring high efficiency. Low 1/ f DCO noise allows the ADPLL to shut down after acquiring lock. The receiver operates in discrete time at high sampling rate (∼10 Gsamples/s) with intermediate frequency placed beyond 1/ f noise corner of MOS devices. New multistage multirate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise, and low power consumption. An integrated on-chip matching network serves to both PA and low-noise transconductance amplifier, thus allowing a 1-pin direct antenna connection with no external band-selection filters. The TRX consumes 2.75 mW on the RX side and 3.7 mW on the TX side when delivering 0 dBm in BLE. Index Terms-All-digital PLL (ADPLL), Bluetooth low energy (BLE), digitally controlled oscillator (DCO), discrete-time (DT) receiver (RX), Gaussian frequency shift keying (GFSK), intermediate frequency (IF), Internet of Things (IoT), low-power (LP) transceiver (TRX), matching network, transmit/receive (T/R) switch, transmitter (TX).

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode.

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for <−107 dBc/Hz in-band phase noise while the 7.3-mW DCO emits −157 dBc/Hz at 20 MHz offset at 2 GHz. Reference spurs are <−91 dBc, while fractional spurs are <−55 dBc. The ADPLL supports a 2-point modulation and consumes 11.5-mW while occupying 0.22 mm 2 . Index Terms-All-digital PLL (ADPLL), digitally controlled oscillator (DCO), time-to-digital converter (TDC), spurs, long-term evolution (LTE), 4G cellular. I. INTRODUCTIONM OBILE phones enjoy the largest production volume of any consumer electronics product. However, the demands they place on monolithic local oscillators (LO), realized as RF PLLs, are particularly tough, especially on integration with digital processors, low area of silicon, low power consumption, low phase noise (PN), and virtually no spurious tones, while being robust against environmental changes. Moreover, as each wireless standard has its own set of specifications, the implementation of a multi-standard PLLs has become a challenging task. For instance, narrow bandwidth systems, such as GSM of 2G and enhanced data rate for WCDMA of 3G, put enormous stress on low out-of-band PN, while wide bandwidth systems, such as 4G/5G, demand Manuscript

This paper presents a digitally controlled frequency generator for dual frequency-band radar system that is optimized for 16 nm FinFET CMOS. It is based on a 21% wide tuning range, fine-resolution DCO with only switchable metal capacitors. A third-harmonic boosting DCO simultaneously generates 22.5-28 GHz and sufficiently strong 68-84 GHz signals to satisfy shortrange radar (SRR) and medium/long range radar (M/LRR) requirements. The 20.2 mW DCO emits-97 dBc/Hz at 1 MHz offset from 77 GHz, while fully satisfying metal density rules. It occupies 0.07 mm 2 , thus demonstrating both 43% power and 47% area reductions. The phase noise and FoMT (figure-ofmerit with tuning range) are improved by 1.8 dB and 0.2 dB, respectively, compared to state-of-the-art.

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