A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13$\ \mu$m CMOS

Abstract

A 1.25 GS/s 6b ADC is implemented in a 0.13 m digital CMOS process by time-interleaving two SAR ADCs with 2.5 GHz internal clock frequency that converts 6 bits in 3 cycles. 5.5b ENOB at 1.25 GS/s and 5.8b ENOB at 1 GS/s are achieved without any off-line calibration, error correction or post processing. The entire ADC consumes 32 mW at 1.25 GS/s including T/H and reference buffers, and occupies 0.09 mm 2 .

15.6 12b 250MS/S pipelined ADC with virtual ground reference buffers

“…In the presented ADC, the buffers replace existing reference buffers, thus incurring insignificant penalty; while off-chip bypass capacitors can be used in conventional circuits to ease the reference buffer requirements [20][21][22], on-chip high-speed buffers are strongly desired in highspeed, high-SNR ADCs to avoid reference voltage ringing [23][24][25]. More detailed analysis of the buffer bandwidth and noise is presented in the next subsection.…”

Achieving Energy Efficiency in Analogue and Mixed Signal Integrated Circuit Design

“…An example of this technique can be found on (Cao et al, 2009), where a 6-bit Timeinterleaving ADC working at 1.25 GS/s without any off-line calibration, error correction or post processing has been designed. The proposed architecture has been implemented using a two time-interleaved SAR ADCs topology combined with flash ADC sub-conversion processes, allowing a reduction from 65 to 6 comparators and lowering its power consumption well below typical values for state-of-art flash ADCs without digital calibration techniques.…”

A 1-V 690 μW 8-bit 200 MS/s flash-SAR ADC with pipelined operation of flash and SAR ADCs in 0.13μm CMOS

“…However, its sequential operation (i.e., one bit per step) limits its sampling rate which is generally undesirable. So far, several structures such as two-bit/step SAR ADCs [1] and time-interleaved ADCs (TI-ADCs) [2] have been proposed to eliminate this limitation. Two-bit/step architectures resolve two bits in each comparison step and thus only require N/2 clocks to determine N bits.…”